Synplicity Introduces MultiPoint Technology

The manufacturer says . . .

Murray Disman says . . .

Synplicity Details New Synthesis Methodology for SoC and Programmable SoC Design New MultiPoint Synthesis Technology Overcomes Hurdles to Designing Large, IP-Intensive ASICs and PLDs SUNNYVALE, Calif.--May 13, 2002--Synplicity, Inc., a leading supplier of software for the design and verification of semiconductors, introduced its new MultiPoint synthesis technology targeting multi-million gate system-on-a-chip (SoC) and programmable system-on-a-chip (PSoC) integrated circuits. By providing a high-productivity design methodology that is scalable to tens of millions of gates, the new technology addresses design challenges that are emerging as application-specific integrated circuits (ASICs) and programmable logic devices (PLDs) become more complex. Synplicity intends to deploy the MultiPoint technology within each of its ASIC and PLD synthesis products, and announced its Synplify ASIC software is the first product to support the MultiPoint synthesis flow. "SoC and PSoC designs are pushing the limits of existing synthesis methodologies, the result being that designers must expend a lot of manual effort managing synthesis flows that can result in long run times and sub-optimal design quality," said Ken McElvain, chief technology officer, Synplicity. "The MultiPoint technology combines the quality of results and ease-of-use of top-down flows with the stability, fast run times, and capacity of a bottom-up flow. By combining the best of existing methodologies with new technology, we believe we are able to deliver an automated high-productivity incremental synthesis solution for large high-performance designs. We also believe the MultiPoint technology is a key milestone in our strategy to deliver the best possible results in the shortest amount of time to both ASIC and FPGA designers." Synthesis Methodology for Complex Designs By combining new technology with the best of existing design methodologies, Synplicity's MultiPoint technology enables a superior methodology for the most critical design flow requirements. Specifically, MultiPoint synthesis provides better quality of timing and area results, faster run time, the ability to handle very large designs, ease of project setup and constraint entry, and intelligent handling of intellectual property (IP) blocks. The MultiPoint technology employs incremental design techniques that enable parts of a design to remain unchanged while others are synthesized. The technology uniquely creates interface logic models (ILMs) based on user-defined compile points, or instructions to the synthesis tool for modeling and synthesizing a particular portion of the design. Unlike other incremental flows where cross-boundary optimizations are difficult, the MultiPoint technology can optimize across design partitions using the same information needed for a top-down synthesis flow, enabling the highest design performance. To address design team productivity, the MultiPoint technology incorporates a unique difference-based incremental synthesis approach. This approach eliminates the need for re-synthesis that is common with time-stamp-based incremental flows by only re-synthesizing design entities that will have a different gate-level netlist due to code or constraint changes. Products that incorporate the MultiPoint technology also can deliver traditional top-down or bottom-up flows, enabling designers the flexibility to implement the most appropriate flow to meet their design requirements. The MultiPoint flow also provides a superior solution to integrating IP into a design due to its ability to automatically model the IP and use the timing information for synthesis. For example, with the MultiPoint technology RTL IP that is instantiated into a design can have logic optimized both inside the IP block and in the adjacent modules without impacting port assignments for the IP core. If it is a hard IP block (i.e., gate-level netlist), the MultiPoint technology will automatically model the IP block, thus saving run time and memory. For designs with replicated logic or IP blocks, the MultiPoint technology allows the designer to control how each unique instance is treated in terms of boundary optimizations, without the run-time penalty of re-synthesizing each instance. SoC and PSoC Design Challenges Drive New Methodology For ASIC designers, the MultiPoint technology delivers a methodology for implementing highly complex designs, at a time when deeper submicron processes are driving typical design sizes above a million gates. According to market research firm Collett International, this year most ASIC designs will be implemented in 0.13 µm or 0.18 µm process technology, and nearly all will include some form of IP or replicated logic. Existing methodologies—top-down, bottom-up, or a hybrid of the two—cannot handle this growing complexity. For example, the traditional bottom-up design flow, or synthesizing lower modules of a design before synthesizing the upper modules, can require many cumbersome scripts and time budgeting, and can inhibit boundary optimization, which leads to sub-optimal design performance. Similarly, synthesizing the design hierarchy all at once in a top-down flow is ideal for delivering the best design performance, but is limited by the memory capacity of the computer, as well as long run times for synthesizing the entire design. Likewise, emerging programmable SoC devices include capabilities such as complex I/Os and embedded processors, and offer up to 10 million PLD-gate capacities. With this increase in complexity come design challenges such as meeting timing and longer run times, and preventing iterations between synthesis and place-and-route. Programmable logic vendors are responding to customer needs with new incremental place-and-route capabilities. Applying an incremental MultiPoint flow to these designs can significantly improve run times for both synthesis and place-and-route.

Synplicity, in addition to describing its MultiPoint design flow, has also announced the use of the technology in the latest release of its Synplify ASIC synthesis tool. Synplify ASIC 2.3 is currently available, and is priced at $115,000 for a perpetual license, and $69,000 for a one-year time-based license. The company claims that MultiPoint technology will be used in all of its products, but it did not provide a schedule as to when the technology will be integrated into its Synplify Pro FPGA synthesis tool. Case analysis has been added to Synplify ASIC 2.3. This feature is said to be useful for the optimization of complex designs, and allows the user to specify constant values to be used on some signals. The rest of the design is then optimized taking those constant values into consideration. According to the company, this feature eliminates the need for slower, less integrated approaches such as using external timing analysis tools or having to set up multiple projects to cover all conditions. Synplicity claims that the 2.3 version of Synplify ASIC has been enhanced to further improve interoperability between the tool and LogicVision's embedded test and Verplex's equivalency checking software. Synplify ASIC software can automatically create assertion files for Verplex's products for formal verification. Flow testing using the LogicVision test products has also been performed during the development of the Synplify ASIC 2.3 software. MultiPoint is described as a hierarchical synthesis methodology for large designs—up to 20 million gates. Two of the problems with today's synthesis tools are the tedious requirements for stitching together blocks of 100K to 200K gates, and the very long compile times. Recent enhancements to Synopsys Design Compiler and software from Get2Chip are claimed to resolve one difficulty by being able to synthesize blocks of more than one million gates. The key elements of the MultiPoint technology are difference-based incremental synthesis and the creation of Interface Logic Models (ILMs) at user-defined compile points. The ILM technique has been around since the mid-1980s, but Synplicity has integrated and automated the technique in this release of Synplify ASIC. ILMs are a partial netlists that is 70% to 80% smaller than the design netlist. Its main benefit is reduced memory requirements, leading to increased capacity and faster compile times. Synplicity claims that it is possible to synthesize complex designs top-down with run times up to 15× faster than a bottom-up design flow. The difference-based incremental synthesis capability allows parts of a design to remain unchanged while others are synthesized. This approach eliminates the need for re-synthesis that is common with time-stamp-based incremental flows by only re-synthesizing design entities that will have a different gate-level netlist due to code, property, or constraint changes. The company now has more than 260 employees, and claims to have sold some 20 seats for Synplify ASIC. Five of their customers have taped out seven designs. Synplicity expects that Synplify ASIC users will tape out 10 more designs this quarter. Most of the designs have been for 0.18 µm, but a number of the newer designs are targeting 0.13 µm processes.

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