Synopsys Introduces RTL Performance Prototyping

The manufacturer says . . .

Murray Disman says . . .

Synopsys Physical Compiler Introduces RTL Performance Prototyping Dramatically Reduces the Time and Iterations Required to Integrate Soft IP into SoCs MOUNTAIN VIEW, Calif.--May 27, 2002--Synopsys, Inc., the technology leader for complex integrated circuit (IC) design, introduced an RTL Performance Prototyping (RPP) flow using Physical Compiler, targeted toward IP providers and IP integrators. Adoption of the new flow enables IP providers to quickly characterize their soft IP against a complete set of end technologies, configurations, and floor plans, and also dramatically reduces the time and effort required to integrate this IP into complex SoC designs. The RTL Performance Prototyping flow allows IP providers to complete a rapid exploration of physical design alternatives early in the design cycle, enabling them to choose an implementation that has the best chance of meeting their target design goals. Traditionally, designers have had to wait until a floor plan was finalized before they could validate the physical implementation feasibility of their RTL and design constraints. However, a floor plan is typically available much later in the design cycle. The biggest benefit of this new flow is being able to use Physical Compiler before a floor plan is available to quickly converge to an implementation that enables predictable and yet faster timing convergence and routability. "RTL Performance Prototyping with Physical Compiler has been valuable in providing our core developers a quick and easy way to get early feedback about the implementation quality of their design," said Christian Folting, engineering manager of MIPS, Inc. "The new capability allows us to do a rapid exploration of physical design alternatives to choose an implementation that has the best chance of meeting the target goals of our designs. RTL performance prototyping has increased productivity and reduced our time to RTL completion." Due to increasing time-to-market pressures and greater demands for design reuse, IP providers are challenged with proving predictable quality of results (QoR) across the hardening of their cores at the customer site. "ARM core developers must be able to rapidly verify the RTL against different physical implementations," said Simon Segars, Vice President of Engineering for ARM. "ARM has already adopted Synopsys' Physical Compiler as the timing closure tool in the reference methodology for our customers. We welcome the introduction of the RTL performance prototyping capability with Physical Compiler to accelerate our process for development and integration of soft IP." When IP underperforms in the customer integration environment, it reduces customer confidence in the quality of IP, and increases time-to-convergence for the final implementation. With this enhanced Physical Compiler flow, developers can explore several different implementation architectures in order to quickly identify and address potential QoR issues prior to customer delivery. This gives IP providers a much higher level of confidence in the implementation feasibility of their IP. "We supply our customers with the ARChitect tool for creating an RTL design according to the user's specification of the configurable ARCtangent processor, plus Design Compiler scripts and some very high level guidelines for floor plan. However, at the customer site, there are enough variables such as actual core configuration, technology, and floor plan used that can make validating our core performance in the customer's integration environment a lengthy, iterative process," said Andy Elms, director of Systems Engineering at ARC International. "As a provider of highly configurable soft cores, ARC expects that the RTL Performance Prototyping flow along with ARChitect will save weeks in the customer validation and integration of our cores." According to Steve Jones, EDA manager, Digital Versatile Disk Division at STMicroelectronics, a developer of soft IP cores, "Using RTL Performance Prototyping allowed our RTL developers to have a high level of confidence in the implementation quality of their design before handing it over to the back-end design team for final implementation and optimization. The floor plan acts as a stepping stone to the use of Physical Compiler early in the design flow, as well as a quality-control check on the physical feasibility of the IP developers' designs. RPP has also been instrumental in substantially reducing IP integration time for our customers." IP integrators can also benefit by adopting an RTL Performance Prototyping flow to verify incoming IP. They can very quickly confirm that the IP they imported can be implemented per vendor specifications. This leads to faster timing convergence and consequently faster time-to-market. "We are responsible for integrating more than 40 soft cores from our IP providers into our chips," said Henry Nurser, design manager, Digital Versatile Disk Division at STMicroelectronics. "In the past, this integration has often been difficult because the physical implementation of the integrated IP failed to meet its timing specifications. When we receive IP characterized through the RTL Performance Prototyping Flow, we have seen a substantial improvement in our time-to-integration." "Over the past two years, Physical Compiler has emerged as the solution to the problem of timing closure that leading-edge design teams worldwide rely on," said Sanjiv Kaul, senior vice president and general manager, Physical Synthesis business unit, Synopsys. "We expect that Physical Compiler's RTL Performance Prototyping capability will now dramatically reduce the time, iterations, and effort required for soft IP characterization, delivery, and integration."

The RPP feature in Physical Compiler creates an initial floor plan of the RTL blocks and IP cores used in a design. Previously, this step had to be performed by the designer before the synthesis operations could begin. The tool or the user can provide information concerning aspect ratio, placement, and pin assignments. Synopsys is targeting the feature at IP developers and IP integrators. ARC, ARM, and MIPS have stated that they intend to use the feature. The IP providers include RPP constraints with the RTL code delivered to customers. The claim is that the RPP flow "dramatically reduces the time and effort required to integrate this IP into complex SoC designs." The 2002.05 release of Physical Compiler, which is to be released in June, will contain the RPP feature.

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