Cadence Introduces CeltIC 4.0

The manufacturer says . . .

Murray Disman says . . .

Cadence Accelerates Signal Integrity Closure With New CeltIC 4.0 Solution for Nanometer IC Design Major New Release Delivers Increased Capacity, Enhanced Performance, and Tighter Design-Flow Integration SAN JOSE, Calif.-- August 12, 2002--Cadence Design Systems, Inc., the world's leading supplier of electronic design products and services, introduced Cadence CeltIC 4.0 for nanometer-scale integrated circuit (IC) design. This new release of the CeltIC signal integrity solution, the recommended crosstalk analysis tool in the TSMC 130 nm reference design flow, includes major enhancements critical to successful nanometer design. CeltIC 4.0 features a greater capacity, with more than five million gates flat to handle the increased scale of nanometer designs. It also demonstrates better performance with its Linux port, and provides even greater accuracy with its ability to model nonlinear slew-degradation effects. Signal-integrity problems are a first-order effect in nanometer designs, where tall, thin wires create unintended electrical effects that impact design timing and functionality. CeltIC 4.0 signal-integrity analysis enables customers to identify these signal-integrity problems before their designs are committed to silicon, and to avoid costly and time-consuming re-spins. Tightened integration of CeltIC 4.0 with Cadence SoC Encounter and Cadence Silicon Ensemble PKS (SE-PKS) provides integrated crosstalk minimization, analysis, and repair throughout customers' IC design flows. CeltIC 4.0 includes support for 32-bit Linux and IBM AIX operating systems, and for 64-bit workstations from Sun Microsystems and Hewlett Packard. Cadence customers AMD, Agere Systems, and Metalink Ltd. have achieved accelerated signal-integrity closure and faster time-to-market with CeltIC. According to John J. Szetela, manager, CAD engineering and systems for AMD's Personal Connectivity Solutions Group, "AMD has used CeltIC for crosstalk sign-off on four tape-outs, including our most recent 130 nm networking design. We are impressed with CeltIC's filtering of false errors, which lets us focus on the few real noise failures, thereby achieving quicker signal-integrity closure on our IC designs. We beta-tested CeltIC 4.0's Linux port, and it demonstrated a 3× speed-up over previous versions. This acceleration should help us get our multimillion-gate designs to market faster." "Agere Systems validates its IC and ASIC designs before tape-out to ensure they are noise-immune," said Kishore Singhal, manager for signal-integrity and interconnect analysis with Agere Systems. "The company has successfully used CeltIC to check and repair crosstalk violations for a number of designs, including our larger, more highly integrated ASIC system solutions. Agere's ASIC business in particular has benefited from the improved accuracy of CeltIC 4.0 in analyzing electrical noise and other problems. Maintaining signal integrity enables us to meet two of our ASIC customers' primary needs: increased high-speed interface channels and reduced time-to-market." "To eliminate costly mask changes and silicon re-spins, it is imperative that our leading-edge DSL chip sets be free from noise problems," said Yuval Itkin, director of the VLSI group with Metalink Ltd. "Using CeltIC allowed us to successfully detect an elusive crosstalk-induced problem in time on our 0.18 µm design. We have incorporated CeltIC into our design flow for crosstalk sign-off of all future designs." CeltIC 4.0 creates crosstalk repair files that drive the in-place-optimization (IPO) engines of SoC Encounter and SE-PKS to implement the fixes. Fixes include re-sizing victim drivers, inserting buffers, spacing aggressors away from victims, and shielding failing nets. CeltIC 4.0 provides greatly increased capacity, and has been used on nanometer-scale designs of more than five million gates flat on standard 32-bit workstations. In addition, CeltIC 4.0 delivers improved accuracy, including modeling the nonlinear slew degradation on victim nets that affects the rise-and-fall delays of the receiver cells. Also new is support for the more accurate BSIM4 and MOS9 device models. "With this new release of the CeltIC signal-integrity solution, Cadence customers will benefit from improved chip yields and performance by addressing signal integrity at all stages of the design flow, including virtual prototyping, block implementation, and final sign-off," said Eric Filseth, vice president of SP&R marketing at Cadence. "The integrated Cadence solution enables our customers to rapidly achieve signal-integrity closure as they progress from RTL to GDSII."

Crosstalk between neighboring wires is a rapidly growing design problem with feature-size reductions below 0.25 µm. The signal wires change shape and move closer together as the feature size is reduced. The wires, which were wide and thin, become narrow and thick. As a result, the total wire capacitance becomes more and more dependent on wire-to-wire capacitance, rather than wire-to-substrate capacitance. This change in the nature of the parasitic wire capacitance can impact circuit delays. In addition, the higher coupling capacitance between adjacent wires can increase crosstalk levels to the point where they have a major impact on the circuit performance. Crosstalk can cause problems when a transition on an aggressor wire causes noise signals to appear on a victim wire. Simultaneous switching on both wires can create crosstalk-induced delay changes that speed up or slow down signals, depending on their phase relationship. There are a number of different approaches that can be used to correct, or at least minimize crosstalk-related effects. These include resizing the drivers or inserting buffers on the victim net to the increase its signal level. The routing can be changed to move the aggressor lines away from the victim nets. Shielding can be used around the aggressor and/or victim wires. This may be the most effective method to lower crosstalk, but it is the least desirable since it limits the wire density. In the past, it had been possible to fix the crosstalk problems manually after they were detected by post-routing analysis. Large designs at the 0.25/0.18 µm node might have tens of crosstalk violations. This can easily increase to hundreds at 0.13 µm and thousands of violations at feature sizes below 1.0 µm. Another approach is clearly required. Cadence has been maintaining that the entire design flow must be aware of these problems as they occur. The company now claims that the "tightened integration of CeltIC 4.0 with SoC Encounter and Silicon Ensemble PKS (SE-PKS) provides integrated crosstalk minimization, analysis, and repair throughout customers' IC design flows." Cadence also makes the point that wire considerations will dominate nanometer-scale designs. The company has written a white paper Down to the Wire that describes concerns and solutions for IC design at the sub-100 nm nodes.

Home    Product of the Week    App Notes    Tech Notes    Newsletters   

		Click here to get your listing up.