LSI Logic Announces RapidChip

The manufacturer says . . .

Murray Disman says . . .

LSI Logic Announces RapidChip—An Innovative Semiconductor Platform New product expected to expand company's customer base by opening up underserved logic market segments, which are expected to exceed $11 billion in 2006 RapidChip halves time-to-market while reducing costs; lowers design and manufacturing risk for high-performance, high-density custom chips First products shipping early 2003 NEW YORK--Sept. 4,2002--Redefining the custom semiconductor market that it was instrumental in creating, LSI Logic Corporation introduced a new semiconductor platform called RapidChip, complete with a new customer-centric design methodology and tool set. Combining LSI Logic's high-performance CoreWare intellectual property (IP) library, customizable logic, and groundbreaking semiconductor design concepts, RapidChip halves the time-to-market, and will permanently change the way complex chips are designed and manufactured. "There is a growing market segment that has evolved as a result of increasing pressure in the industry to create high-density chips faster, more predictably, and at a lower cost," said Jordan Selburn, principal analyst, iSupply Corporation. "Application-focused design platforms that incorporate rapid customization will relieve these growing pressures, and will provide an enabling capability to seize this new segment." The time from design start to product delivery for RapidChip is approximately six months, which is comparable to a Field Programmable Gate Array (FPGA), but is about half the time of a standard-cell Application Specific Integrated Circuit (ASIC). Unit prices for RapidChip can be as low as 10% of a complex FPGA, and total development costs can be as low as 20% of a normal standard-cell ASIC. Another benefit of this new low-risk platform is the ability to quickly migrate a design to a full ASIC to achieve the lowest possible unit price. "RapidChip is specifically targeted at the emerging middle of the logic TAM that is largely underserved," said Wilfred J. Corrigan, LSI Logic chairman and chief executive officer. "RapidChip employs our extensive library of proven intellectual property building blocks to address the demands of new communications, consumer, and storage customers requiring lower silicon development costs and faster time-to-market." The first RapidChip products are in design today, and will be manufactured early next year using LSI Logic's G12 and Gflx (0.18 and 0.11 µm) process technologies at its world-class Gresham, Oregon, manufacturing campus, and at its foundry partners. G90 (90 nm) versions of the new technology will be available for customer engagements in late 2003. RapidChip will be available to LSI Logic customers through its direct sales channels and worldwide distribution partners. "Our customers need the ability to configure their chips quickly with increased predictability at a lower cost," said Rick Marz, LSI Logic executive vice president of Communications and ASIC Technology. "RapidChip provides a quick, deterministic design cycle with access to high-value IP that is proven, tested, and pre-placed." This new platform product combines the high-density, high-performance, and proven IP benefits of cell-based ASICs with the customization and fast time-to-market advantages of FPGAs. The resulting combination considerably reduces the design-through-production cycle. This is achieved through families of market-specific silicon platforms that have been predefined and prefabricated to enable easily customizable designs. The ease-of-use and customization is realized through the methodology and user-defined metal layers. Unique to RapidChip is the customer-friendly interface that dramatically simplifies the underlying complexity of the design tools and flows associated with SoC design. Rule sets automatically manage architectural design, verification, and physical design. As a result, design schedules for high-performance chips are very predictable. "As the pioneer of standard-cell ASICs and SoC design methodology, LSI Logic is uniquely qualified to bring this revolutionary product to market," said Chris Hamlin, chief technology officer for LSI Logic. "No other company has our end-to-end experience for an initiative of this magnitude. RapidChip represents a whole new design era and is destined to become the technology of choice."

LSI Logic is positioning RapidChip between FPGAs and cell-based ASICs in the time-to-market, development expense, and part-cost three-dimensional continuum. The company's basic approach is to provide a silicon platform for other IP and customer logic by providing a substantial amount of embedded resources and a gate array section with three- to eight-million-gate capacities. The gate-array section of the device can be customized using four metal layers. LSI intends to introduce a number of different platforms for communications, storage, and consumer applications. The embedded resources will match the application, and will usually include an RISC and/or DSP processors, three to ten Mbits of memory blocks, PLLs, and metal-configurable I/Os that include high-speed differential pairs. Other embedded elements could include interface circuitry, SerDes, multipliers, MACs, FIFOs, multi-ported SRAM, etc. LSI Logic is not alone in this effort to provide the time-to-market and development cost advantages of FPGAs, but at a lower production cost, especially for the higher density FPGAs. The possibility of reducing device costs by more than $1000 per part is attracting substantial attention. NEC electronics has already introduced two products aimed at the same market. These are its SoCLite and Instant Silicon Solution Platforms (ISSPs). Both of these ASIC products are aimed at much simpler designs than LSI's RapidChip platform. SoCLite contains an embedded ARM7TDMI processor, 2 Kbytes of boot ROM, 8 Kbytes of SRAM, a variety of peripherals, and 190K gates for user defined logic. The ISSPs have a somewhat different architecture in that configurable modules are used instead of gates for the user-defined logic. NEC's first family of modular-array ISSPs is being produced using the company's 0.13 µm UX4 process. This series contains three members with rated logic capacities of 227K, 530K, and 1109K gates. Each of the basic cells contains multiplexer-based logic and a register. The largest part in the series contains some 60K registers. The company plans on expanding the ISSP line in early 2003 with two new families. One will include an embedded processor core, and the other will include Gbits/s I/Os. The I/Os in the current ISSP family can be mask-programmed for 3.3 V or 2.5 V, HSTL, SSTL, or 622 Mbits/s LVDS signals. The ISSP devices can be customized with two to three metal layers, and contain extensive BIST circuitry. Expected NREs are in the $50K to $100K range. The claim for both the LSI and NEC approach is that the device, in wafer form, can be built and stocked without the final metal layers. As a result, turnaround times will be in weeks. NEC estimates that the density of its ISSPs will be one-third to one-quarter of a cell-based ASIC. It expects prices to be about $35 each for the 200K part, and about $150 for the largest device in the family. Even though NEC is targeting designs with volumes between a few thousand and 100,000 units, it will be economical to replace high-density, multi-thousand dollar, FPGA designs for volumes of a several hundred units. Other companies that offer Modular-Array ASICs with embedded resources include AMI Semiconductor, Chip Express, eASIC, Fujitsu Microelectronics, and Lightspeed Semiconductor. The HardCopy devices from Altera can be classified as Modular Arrays, but are only capable of converting designs for Altera devices. AMI is making its XPressArray parts using a 0.18 µm process at TSMC. AMI customizes its devices with two metal layers that are applied in-house. Chip Express is now using a 0.25 µm process. Both LSI and NEC are offering parts using more advanced processes. The two largest FPGA producers, Altera and Xilinx, offer low-cost alternatives for their devices. Altera's HardCopy, a mask-programmed version of the FPGA, is now available for its larger APEX devices, and will be available for the company's Stratix parts. Xilinx recently introduced its EasyPath low-cost migration option. The Xilinx approach depends on yield increases for specific customer designs that do not use all of a device's resources. LSI has been somewhat vague on the resources that will be included in specific platforms, but it seems clear that the company intends to pursue the more complex SoC designs. The company has stated that its part will have three to ten million user-definable ASIC gates. This is substantially more logic capacity than is available from any FPGA. At this level of complexity, cell-based ASIC development programs can easily cost $10 million, with a majority of the effort spent on verification. This makes it very hard to accept LSI's statement that, when using RapidChip, "total development costs can be as low as 20% of a normal standard-cell ASIC." The NRE may be 20% of a cell-based ASIC, but there is no way that the total development cost will be that much less.

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