Tenison Introduces VTOC

The manufacturer says . . .

Murray Disman says . . .

Tenison EDA Bridges SoC HW/SW Co-Design Gap CAMBRIDGE, U.K.--Sept. 23, 2002--Tenison EDA introduced a commercial version of VTOC, its Verilog-to-C translator optimized for the hardware-software co-design issues facing SOC design teams. More information on VTOC and a free evaluation copy is available online at www.tenison.com. By using the tool to create a cycle-accurate model in C, C++, or SystemC, the design team can perform myriad tasks to improve the speed and quality of any SoC design according to Dr. Jeremy Bennett, CEO of Tenison EDA. "The world works in Verilog," Dr. Bennett said. "Introducing another HDL is unnecessary, but there are a great many reasons to convert that code to C." Dr. Bennett explained that the software portion of a modern SoC has passed 50 percent of the total time and effort expended on design, and all of that activity takes place in C. "Providing the software designer with a cycle-accurate model in C that is converted from a reliable Verilog description makes perfect sense." By working with this model, software engineers no longer have to wait for actual silicon prototypes from the fab before beginning their work. In addition, the C-language model can be used for high-speed simulation and hardware acceleration, and provides a handy method for generating easily portable intellectual property models. Customers Chime In "VTOC has been instrumental in reducing development costs and time-to-market," said Martin Jackson, chief technical officer of communications processor powerhouse Globespan Virata. "We had extremely positive results using VTOC to develop our last communication processor." Price/Availability VTOC is available now with a base price of $56,000. A version of the product for VHDL to C translation is currently under development. For additional product and sales information, visit www.tenison.com.

Tenison EDA is another startup attempting to commercialize an academically developed design tool. The company spun out from the University of Cambridge Computer Laboratory in 2000. Its first product, VTOC, a Verilog-to-C translator, has been under development for five years, and has been in beta at 12 customers for two years. VTOC accepts the hardware design expressed in synthesizable Verilog and converts it to cycle-accurate C, C++, or SystemC. Tenison envisions three model-creation roles for the VTOC tool. These are in SoC development, by IP developers, and for those migrating to SystemC. SoC developers and those migrating their design environment to SystemC can use VTOC to translate legacy or new HDL designs or third-party IP to cycle-accurate C/C++/SystemC models. These models allow system designers to evaluate architectural alternatives and optimize their approach. In addition, the impact of hardware design changes on the total system performance can be assessed continuously during the development program. VTOC can be particularly useful to companies developing and selling IP cores. It is almost always necessary for these firms to provide a C-based model of the IP that potential customers can use to evaluate the IP, and that actual customers can use in running system-level simulations. Tenison EDA has produced a white paper, Hardware/Software Co-Design in the SoC Era, that describes the role and benefits of VTOC in SoC development.

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