Cadence Introduces SoC Encounter 2.2

The manufacturer says . . .

Murray Disman says . . .

Cadence Introduces Single-Architecture Encounter System for Nanometer Design Integrates Best-in-Class Technologies to Support Full-Chip Continuous-Convergence Design Methodology SAN JOSE, Calif.--Sept. 18, 2002--Cadence Design Systems, Inc., the world's leading supplier of electronic design products and services, introduced the Cadence Encounter RTL-to-GDSII architecture for nanometer-scale digital design implementation. The Cadence Encounter system combines silicon virtual prototyping and detailed IC implementation into a unified architecture with a single in-memory data model and user interface. All Cadence SoC Encounter customers will be upgraded to version 2.2, which is based on the new architecture, and leverages best-in-class nanometer technologies, including the NanoRoute graph-based routing engine and CeltIC signal-integrity analyzer. Cadence is also introducing Nano Encounter, a new lower cost product configuration that supports nonhierarchical designs up to 10 million gates. SoC Encounter and Nano Encounter support a continuous-convergence methodology in which design teams get full-chip detailed design implementation—including detailed routing—the first day of implementation and every day thereafter. The Encounter system is the first design architecture with the performance and capacity to deliver daily full-chip, full-wire iterations for massive nanometer designs. This wires-first approach enables design teams to always know the status of their design relative to its performance goals, to always work on the highest priority portions of the design, and to make systematic, predictable progress toward tapeout. "The Cadence Encounter architecture is designed from the ground up to focus on the core issue in nanometer digital implementation—delivering the best wires," said Lavi Lev, executive vice president and general manager, Cadence IC solutions business. "Nanometer success will require staying as close as possible to silicon, which means moving to a wire-centric continuous-convergence design methodology that is inherently efficient and predictable." Definitive Customer Success "We beta-tested SoC Encounter 2.2, and as a long-time Silicon Ensemble customer, we're pleased with Cadence's direction and progress in nanometer IC implementation," said Kazuyuki Kawauchi, general manager, Technology Development, LSI group, Fujitsu Limited. "Cadence has integrated a great deal of advanced technology into a fast, lightweight system with compelling advantages in terms of performance, capacity, and support for cutting-edge design practices. We expect to develop a lot of nanometer chips using SoC Encounter." "After an extensive evaluation, Agilent Technologies' Networking and Computing ASIC Products Division has deployed SoC Encounter 2.2 in our nanometer design flow," said Richard Nash, High-Performance VLSI Design Automation manager. "Providing full-chip timing and routing congestion feedback early in the design cycle improves schedule predictability and time-to-market, and also reduces overall chip design investment. The successful incorporation of SoC Encounter into our methodology is another direct benefit of our engagement with Cadence." "S3 has successfully designed and taped-out a six-million gate multimedia chip in nanometer process geometry using the Encounter-to-NanoRoute flow," said Michael Shiuan, vice president of engineering, S3 Graphics. "The combination of the Encounter platform and the NanoRoute router provides impressive speed and capacity. We were able to route the chip flat, which not only simplified our physical analysis and design flow, but also helped us contain die size." According to Yoshito Muraishi, deputy general manager of Kawasaki Microelectronics, Inc., Products Development and Design Department, "Kawasaki Microelectronics and Kawasaki LSI have used the Encounter-to-NanoRoute flow on multiple tapeouts at 130 nm and other silicon geometries, including first-silicon success at 330 MHz. The new Cadence SoC Encounter 2.2 provides the speed, capacity, and cross-talk optimization needed for our next-generation designs. Its hierarchical design capability is excellent. With SoC Encounter, we could dramatically reduce turnaround time for multi-million-gate designs." Cadence Encounter Roadmap SoC Encounter and Nano Encounter version 2.2 are available immediately, with the unified First Encounter-based user interface, CeltIC signal-integrity prevention and correction, and NanoRoute nanometer routing capability. Encounter architecture integration will be complete and shipped in production by the end of 2002, including OpenAccess support, with ongoing enhancements available thereafter. Cadence is offering attractive upgrade paths, including master-key backward compatibility, for all customers with its Silicon Ensemble family products. Pricing and Availability The Cadence SoC Encounter hierarchical IC implementation solution, Cadence First Encounter Ultra, and Cadence Nano Encounter are available immediately for Sun Solaris and HP's HP-UX UNIX operating systems. One-year U.S. list prices start at $595,000, $350,000, and $375,000 respectively. For information about upgrade paths for customers, or for international pricing, please contact a local Cadence office.

Cadence continues to add features and capabilities to SoC Encounter, which is a follow-on to its Silicon Ensemble design system. The company introduced version 2.1 in March of this year, and now follows with version 2.2. Version 2.3 will be introduced during 4Q02, and will be an integrated system using the OpenAccess data. The final version of SoC Encounter will have 90 nm foundry support, a 50+ million gate capacity, and a Linux option. The Silicon Ensemble Platform was targeted at 0.35 to 0.18 µm designs, while SoC Encounter Platform is meant to be used with 180 nm to 90 nm processes. Cadence plans on releasing Encounter Platform 70/50 in the 2003/2004 time frame for designs at 70 nm and below. Encounter Platform 70/50 will have a capacity of more than 100 million gates, and will employ subwavelength-aware place-and-route techniques. The current release of SoC Encounter includes the production version of NanoRoute, the graph-based routing technology that Cadence got with its acquisition of Plato Design Systems earlier this year. The company claims that NanoRoute is the critical enabler for high-capacity flat designs of up to 10 million gates and up to 50 million gates for hierarchical designs. Cadence further claims that the use of NanoRoute has led to a five to ten times increase in both the capacity and speed of the tool. Another important addition to the tool is the integration of the company's CeltIC signal-integrity tool. CeltIC is used throughout the RTL-to-GDSII flow to identify and, at the user's option, repair signal-integrity violations. Cadence describes its flow as a "wire-centric continuous-convergence design methodology."

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