Synopsys Introduces BIST

The manufacturer says . . .

Murray Disman says . . .

Synopsys Introduces New Logic BIST Capability to Significantly Reduce Test Cost SocBIST Delivers Identical Fault Coverage with 10 Times Reduction in Test Time and 400 Times Reduction in Data Volume Compared to Full Scan MOUNTAIN VIEW, Calif.--Sept. 30, 2002--Synopsys, Inc., the technology leader for complex integrated-circuit (IC) design, announced its entry into the logic BIST market, with DFT Compiler SoCBIST offering deterministic-logic BIST capabilities. Compared to full scan, SoCBIST provides designers significant savings in test cost by reducing test time and data volume, while deterministically retaining scan's very high fault coverage. It is transparently integrated within Synopsys' physical-synthesis flows, thereby ensuring designers that design-for-test (DFT) closure and timing closure are always achieved. "NVIDIA has long recognized the limitations of traditional test methodologies as applied to high-volume products with the performance levels and device sophistication of our graphic and platform processors," said Chris Malachowsky, co-founder and vice president of hardware engineering at NVIDIA Corporation. "Our adoption of Synopsys' SoCBIST overcomes these limitations, allowing us to improve test coverage while simultaneously reducing the cost of test. Our first application of this technology was on a 20-million-gate device. The results have exceeded our expectations, showing off both the capability and maturity of this innovative new DFT platform." "We have seen excellent test data volume and tester time reduction with Synopsys' SoCBIST—from RTL synthesis to gate-level diagnostics—and are very satisfied," said Seiichi Nishio, senior manager, System LSI Design Division, Semiconductor Company, Toshiba Corporation. "SoCBIST is a straightforward extension of the Synopsys DFT Compiler and TetraMAX ATPG design flows we use. We will use SoCBIST in upcoming ASSP products, and intend to deploy SoCBIST within Toshiba design teams." To meet strict product quality mandates without increasing the cost of design and test, designers need a DFT solution that provides predictable high-fault coverage, requires minimal automatic test equipment (ATE), and does not impact the overall design flow. Synopsys' SoCBIST meets these requirements, reducing tester time by more than 10 times and reducing data volume by 100 to 400 times compared to traditional scan. Additionally, SoCBIST needs 20 or fewer ATE pins, and requires less than 1 percent of the vector memory required by a full-scan approach. SoCBIST is transparently integrated within the Synopsys Design Compiler and Physical Compiler flows. It is an extension of Synopsys' unique 1-pass test synthesis flow, which enables designers to use SoCBIST directly within the physical-synthesis environment. This eliminates costly iterations between design synthesis and test implementation, and enables IC designers to achieve timing and DFT closure simultaneously. In addition, SoCBIST provides comprehensive and easy-to-use design rule-checking and validation features, as well as powerful BIST integration, verification, diagnostic, and debug tools. "Our customers are faced with the conflicting demands of producing the highest quality products while reducing their overall test cost, and they are looking to us for a solution," said Antun Domic, vice president and general manager of Synopsys' Nanometer Analysis and Test business unit. "Since SoCBIST is integrated within the industry-standard Synopsys synthesis flow, we enable our customers to preserve their existing investments in design and test automation tools, and still achieve higher quality results at a lower cost." Pricing and Availability SoCBIST is an add-on to DFT Compiler, and will be available in a controlled-availability basis with the September, 2002, production release. Pricing for the DFT Compiler SoCBIST add-on begins at $175,000 US list price for a one-year technology subscription license (TSL).

Synopsys has rounded out its test solutions with the addition of DFT Compiler SoCBIST, a logic built-in self-test tool, to the company's DFT Compiler and TetraMAX ATPG tools. SoCBIST is an add-on to DFT Compiler, and is integrated within Design and Physical Compiler synthesis flows. In the test area, Synopsys also offers BSD Compiler, a tool for the synthesis and verification of boundary-scan logic. BSD Compiler operates within Design Compiler, and uses JTAG components from the DesignWare library. The tool automatically creates a boundary-scan description language file for board-level test, and generates functional and DC parametric vectors for manufacturing test. According to the company, SoCBIST was introduced to overcome the rapidly growing cost of conventional scan-based testing with increasing chip complexity. Test costs can be a significant part of the production cost of producing an ASIC. These cost are directly related to the amount of time that the part must spend connected to a very expensive tester. The amount of time on the tester depends on the number of test vectors applied to the device and on the speed of loading the vectors. It is the number of vectors required to insure a specified quality level that has exploded with chip complexity. Goals that Synopsys set for and met with SoCBIST include support for a large number of parallel internal scan chains to reduce test time by an order of magnitude, and compressing the scan-test data to reduce the test-data volume by at least several orders of magnitude. In addition, the approach also yields a significant reduction in the number of test pins needed.

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