Telairity's New ASIC Approach

The manufacturer says . . .

Murray Disman says . . .

New Approach to ASIC or ASSP Development from Telairity Semiconductor, A Fabless ASIC Company Howard Sachs, President/CEO and industry veteran, introduced a new development environment delivering from 2 to 10× productivity improvement and a 2× speed improvement over current methods. SANTA CLARA, Calif.--Oct. 21, 2002--Telairity Semiconductor Inc., a fabless ASIC company, announced the Telairity Speed-Optimized (TSO) design environment that provides a new approach to high-performance ASIC design. The TSO design environment eliminates most of the problems associated with timing closure and signal integrity in ASIC design when using deep-submicron (DSM) process technologies, and can achieve a 2× performance improvement over conventional methods. The key to the TSO ASIC design environment is an extensive gallery of pre-engineered, pre-verified IP building blocks. Each IP building block has approximately 1000 logic gates. The design and layout of the blocks is completed with a custom methodology that results in designs optimized for high speed. The TSO environment eliminates signal-integrity issues such as crosstalk so that customers have "proven," highly reusable IP building blocks. Any digital design can be created with these blocks, 75 percent of which are generic and 25 percent are market-specific. "I have spent years with Fujitsu and other semiconductor companies solving COT and ASIC design problems and, as President of the Virtual Socket Interface (VSI) Alliance, I worked with the top semiconductor, EDA, and system companies to solve design reuse issues," said Howard Sachs, President/CEO of Telairity. "Those experiences ultimately led me to realize that it was time to look at the ASIC, synthesis, and DSM challenges from a new approach—an approach that would allow engineers to develop complex chips in a much shorter time without sacrificing performance or area. Instead of fixing the shortcomings in existing design tools, the TSO design environment fixes the problems of timing closure and signal integrity up front, and provides designers with reusable hard IP building blocks and the methodology and tools to support this solution." Engineers can develop complex, high-speed designs using pre-engineered blocks referred to as groups and SGEM point tools from Telairity. With Telairity's ASIC solution, designers no longer have to deal with the time-consuming problems of crosstalk. Careful design and layout of the groups, the small size of the groups at less than 1000 gates each, and the fact that connections for each group are completely contained with the first three wiring layers eliminates local-wiring crosstalk. M4 and M5 crosstalk is dealt with easily with existing tools that identify the aggressors and victims, and provide enough spacing to eliminate the problems. Telairity has produced a 400,000-gate test chip using fewer than 50 unique groups to implement a SISD FIR filter, a SIMD FIR filter, and a SIMD FFT. This first test chip was used to verify the group IP as well as the methodology and the CAD flow. This design went from floor plan to GDSII in one day. New groups are being developed constantly to implement other algorithms. Telairity anticipates a gallery of approximately 1000 pre-verified groups in less than one year. A second DSP test chip, targeted for pre-production release in December, 2002, on UMC's 0.18 µm process will operate at more than 400 MHz and will achieve a density of better than 50K gates/mm².

Telairity is developing a really new way to design and build ASICs. It is a cell-based ASIC, but the cells are unlike any currently in use. Today's ASICs are built using a library of relatively simple cells such as gates, registers, and buffers. Telairity's basic cell contains 500 to 5K gates, all custom-designed to perform a specific function. These large basic cells, called groups or hard IP cores by the company, and its design flow lead to its performance and productivity claims. The company claims a 2× speed improvement over most synthesized designs. It says that 400 MHz+ designs are easily achievable at 0.18 µm. Possibly more important than the improvement in performance is the claimed increase in productivity. The claim is a 2× to 10× productivity increase over a typical synthesized design—the higher the clock rates, the higher the productivity increase. Telairity is a fabless ASIC startup with an initial concentration on medium- to high-speed ASICs and ASSPs for use in DSP applications. It intends to broaden its activities to include devices with embedded processors and those for use in switches and network processing as it gains experience and size. The first family of cells is designed for high-clock-speed ASICs. The company also plans to develop cells for low-power and time-to-market designs. Telairity developed its approach by studying the reuse patterns of different-sized blocks in ASIC designs. As might be expected, it found very high reuse for cells and macros with complexities of up to 100 gates, and very low reuse for large blocks with more than 50K gates. What was surprising was that there was still a significant amount of reuse for blocks with up to 5K gates. The company expects that 1000 different groups, which are custom-designed supermacros, will be required to implement designs for most applications. Telairity has completed about 50 groups, and hopes to increase this to 100 early next year. According to the company, this number of groups will enable it to complete certain designs. Groups that are needed for a specific project can be designed by the customer or by Telairity. Each group contains clock circuitry, scan chains, and input/output registers. In addition to the complex groups, Telairity has designed what it calls trailers that contain clock and signal buffers, and can be placed between groups as needed. The key to the design flow is the floor planning and placement of the groups, running the interconnect, and then making the area, speed, and power estimations. The first three metal layers are used for local wiring within each group. The claim is that crosstalk problems within the group have been eliminated. Global wiring is done with M4 and M5. According to the company, crosstalk from global to local wires is eliminated by the natural spacing. Crosstalk between global wires must be dealt with by the designer by placing the groups or by using shielded pairs. The company is willing to operate under the traditional ASIC model, the COT model, and/or the design services model. It will be very selective in accepting design-services type engagements, and prefers the ASIC or COT approaches. Telairity plans to engage with its first alpha customer in 1/03, and with a second customer in 3/03. It expects to be able to enter into multiple customer engagements by 7/03.

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