LSI Announces Wire-Bond Advance

The manufacturer says . . .

Murray Disman says . . .

LSI Logic Next-Generation Wire-Bond Packaging Technology Enables Smallest Chip Designs in Copper/Low K Silicon Pad on I/O offers best-in-class signal I/O density, up to 50% die-area reduction, and reduced costs for ASIC/SoC/RapidChip designers. MILPITAS, Calif.--Oct. 21, 2002--LSI Logic Corporation introduced Pad on I/O, an industry first for copper/low K processes in wire-bond packaging. The LSI Logic Pad on I/O technology places bond pads directly on top of active I/O circuits in a chip design. Pad on I/O was developed for the LSI Logic Gflx (0.11 µm) and G90 (90 nm) silicon technologies. The Pad on I/O technology provides ASIC/SoC/RapidChip platform designers with the industry s most cost-effective chip design by reducing die area up to 50 percent when compared to standard wire-bond designs. The company designed robust bond pad structures and metal stack-up schemes to ensure that the mechanical integrity of the silicon chip is not compromised. The enhanced silicon design features allow LSI Logic to use industry-standard wire-bond equipment, resulting in cost-effective high-volume assembly. "LSI Logic's Pad on I/O technology, especially for high-performance copper die, has the potential to significantly extend the use of low-cost wire bonding over flip chip," said Neil Moskowitz, senior analyst at Prismark Partners LLC. "Increasing interconnect density, power, and ground access to die center, and increasing silicon utilization are some of the potential benefits of this technology." "LSI Logic created an innovative packaging technology that allows system-on-a-chip designers to take full advantage of geometry shrinks in Gflx (0.11 µm) and G90 (90 nm). The result is a chip design that maximizes silicon area while maintaining cost-effectiveness," said Maniam Alagaratnam, vice president of package development for LSI Logic. "Our engineering teams continue to exhibit tremendous technical prowess by developing this capability in copper/low K as well as an assembly process for reliable wire bonding on top of active circuits." Pad on I/O can be used for in-line or staggered-pad designs. For staggered-pad designs, LSI Logic offers ASIC/SoC/RapidChip designers the option of designing up to three rows of staggered pads. Pad on I/O provides a staggered pad pitch of 27 µm effective when compared to the industry-standard two-row staggered-pad approaches. All standard packages offered by LSI Logic have been optimized to fully use Pad on I/O. "As the industry leader in system-on-a-chip solutions, LSI Logic continues to take the communications, consumer, and storage markets into new areas by developing leading packaging technologies and innovations," said Stan Mihelcic, manager of Advanced Packaging Solutions, Technology Marketing, LSI Logic Corporation. "With the advent of 110 nm and 90 nm silicon processes, packaging is being challenged to keep up with density increases and resulting die-size reductions in silicon design. With LSI Logic's advanced silicon process technologies, Gflx and G90, Pad on I/O provides robust design solutions, resulting in the most cost-competitive ASIC/SoC/RapidChip designs in the industry." Pad on I/O is available now, and is used for all wire-bond designs in Gflx and G90 silicon designs.

The primary benefit of reducing feature size is that more functionality can be included on the same size die and/or the size of the die can be reduced, thereby reducing its cost. However, a limit on die-size shrinking occurs when the size is determined by the room needed for the bonding pads and not for the circuitry on the chip. This condition is called "pad limited," and is occurring with increasing frequency at the 0.13 µm node. A number of approaches are being used to get around the pad-limited restriction. The most advanced technique is flip-chip assembly where the bumps are spread across the surface of the die. Flip-chip assembly is primarily being used for high-I/O-count devices and for those parts with high-speed requirements since the method greatly reduces the inductance associated with wire bonding. The major drawback to flip-chip assembly is cost, which can reach twice that of a wire-bond-assembled device. Flip-chip packaging is used more and more as the feature size is reduced. LSI claims that 35% of the designs for its 0.18 µm process and 67% of the designs for its 0.11 µm process use flip-chip assembly. Over time, the wire-bond pad size and spacing have been reduced to increase the pad density. This has almost reached a limit because of the size of the bonding wire. Another technique that is used in most small ASIC designs is staggered-bond pads. This, in effect, results in two rows of bonding pads around the periphery of die. Additional silicon is needed for the second row. As a result, the staggered-pad approach does not quite increase the pad density by a factor of two. LSI's Pad on I/O technique adds a third row of pads. The important difference is that this row of pads is placed over the I/O circuitry and doesn't add to the die size. The company claims that the pad does not affect the performance of the I/O circuitry. This seems to be true only for relatively low signal speeds. The Pad on I/O method cannot be used over high-speed SerDes circuitry or where differential I/Os are used. LSI is working on extending the Pad on I/O approach to accommodate differential I/Os.

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