Mentor Collaborates with Sharp

The manufacturer says . . .

Murray Disman says . . .

Mentor Graphics Announces Technology Collaboration with Sharp Corporation WILSONVILLE, Ore. and OSAKA, Japan--Oct. 31, 2002--Mentor Graphics Corporation announced a technology partnership with Sharp Corporation that provides Mentor Graphics with access to "hardware compilation" technology, known publicly as the Bach system, for the rapid design and optimization of embedded systems. Development teams from Mentor Graphics and Sharp will work together to merge co-verification and hardware compilation technologies to create a new set of design optimization and analysis tools for embedded system and SoC designs. "This partnership advances our development of system-on-a-chip design and verification tools beyond the traditional capabilities of the Seamless tool, our flagship co-verification product," said Serge Leef, general manager of the System-on-Chip Verification Division at Mentor Graphics. "Combining hardware compilation of portions of the design with advanced system integration and co-verification technologies will result in truly unique product offerings starting in 2003." The hardware-compilation technology from Sharp allows abstract descriptions of hardware in C to be simulated and synthesized into RTL. This can be combined with the Mentor Graphics Seamless C-Bridge technology to enable efficient system-level co-verification of designs that include both C and HDL representations of hardware and embedded software. This hardware-compilation technology was jointly developed by Sharp Laboratories of Europe (SLE) and Sharp Corporation. It has been used by Sharp on over 20 successful ASIC and FPGA design projects, with over half a dozen successful ASIC tape outs. "It is exciting to see that our technology will be available outside of Sharp," said Dr. Kambe, deputy division general manager at Sharp's Elemental Technology Development Center, Integrated Circuits Group. "This three-way collaboration between development teams in the U.S. (at Mentor Graphics) and in Japan and the U.K. (at Sharp) will result in a design environment that allows designers to create complex system-on-chip designs much more quickly and easily." "Combining Seamless and Bach will provide designers with a new approach to embedded system design," said Dr. Paul Boca, research supervisor at Sharp's research laboratory in Europe. "Starting from a description in untimed behavioral C, designers will be able to explore different hardware/software partitions using Seamless co-verification technology from Mentor Graphics and efficiently compile hardware blocks to circuits with our hardware compilation technology." About Seamless Combining the best in embedded software development tools with logic simulation, the Mentor Graphics' Seamless co-verification environment delivers high-performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be carried out in parallel, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as RTOS initialization, block memory transfers, and algorithmic routines. Seamless with C-Bridge further boosts performance through incorporation of C hardware descriptions. Seamless supports all popular logic simulators and software development environments, including the Model Technology ModelSim environment.

Well, here's another attempt at C-based hardware design. The desire to reach this goal is understandable. C is used extensively for processor programming, signal-processing algorithm development, system design and verification, and test-bench development. It would be nice to avoid the manual conversion of system specifications and algorithms to Verilog or VHDL for hardware implementation. Two trends are making automatic C-based hardware design more and more attractive. One is the conversion of processor-based signal-processing algorithms written in C to hardware to accelerate their execution times. The other is coming from the integration of processors and FPGAs, a relatively new trend, and/or the integration of processors and logic in an ASIC, which has been going on for some time. The decisions as to how to partition the functions in the integrated processor/FPGA systems between the hardware and the processor software is now done manually based on the experience of the system designer. It would be convenient to be able to evaluate these choices quickly to arrive at an optimum partition. Mentor's Seamless and C-Bridge are tools that are often used in the evaluation or hardware/software co-verification process, which explains the company's interest in C-based hardware design. There are some basic problems with using C for hardware design. According to a recent article from Quicksilver Technology by Dave Pellerin, Where C Language Design Fits, "C language does not provide that level of abstraction (which we call RTL), so 'C-based' languages for hardware design must add cumbersome RTL-like constructs such as syntax decorations, extra functions, or keywords, compiler hints and more, to create some meaningful abstraction. Without such an abstraction, the developers of C compilers for FPGAs and other nontraditional targets face a nearly impossible problem—how to efficiently map algorithms and applications written for one class of processing target (the traditional microprocessor) to something entirely different (arbitrary logic gates and registers). Nobody has yet figured out how to do that mapping with a reasonable level of efficiency." One reason given in the article is that "any good programming language provides one important thing: a useful programming abstraction of its target. VHDL and Verilog (or more specifically, the synthesizable subsets of these languages) succeed very well because they provide a rational, efficient abstraction of a certain class of hardware—level- and edge-sensitive registers with reset and clock logic, arbitrary logic gates, and somewhat larger clocked logic elements arranged in a highly parallel manner. Nearly all of today's FPGAs fit this pattern, and it is the pattern also found in the vast majority of today's ASIC designs, no matter how complex." Another new entrant in the C-based design area is Future Design Automation (FDA). This Tokyo-based company was started in 2000, and now employs 20 people. It has recently announced North American headquarters in California. It is planning a formal release of its SystemCenter design tools in January, 2003. The company is targeting algorithm developers and system designers rather than the traditional ASIC engineer. ASIC designers are generally satisfied with Verilog/System Verilog, and show little inclination towards using C-based design techniques. Like Sharp's Bach tool, SystemCenter converts C code to HDL. Rather than specialized libraries, SystemCenter relies on the use of comments and directives embedded in the ANSI C code to control synthesis and partitioning. The company claims that the resulting designs will be some 20% less efficient in terms of area and or speed. The benefit claimed by FDA is that design cycle times can be cut in half.

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