New Physical RTL Flow from LSI Logic

The manufacturer says . . .

Murray Disman says . . .

Faster, More Predictable Chip Design with New Physical RTL Optimization Flow from LSI Logic Innovative Physical RTL Optimization (PRO) Flow Results in Highly Predictable Design Closure and Shortened Time-to-Market MILPITAS, Calif.--Nov. 18, 2002--LSI Logic Corporation announced its unique Physical RTL Optimization (PRO) flow, developed to identify physical design issues early in today's complex System-on-a-Chip (SoC) design cycles. LSI Logic is the first in the industry to directly link routing and congestion problems in physical design back to the RTL code while the code is still being developed, allowing engineers to quickly and predictably resolve major physical design issues at the RTL stage. By minimizing the number of iterations between logical and physical design, the LSI Logic PRO flow allows engineers to be confident in achieving predictable design closure and meeting crucial time-to-market windows. "Our customers require increasingly complex, high-performance, high-density designs in Right-First-Time, On-Time silicon, and our ability to provide quick feedback is immensely helpful to design engineers," said Jeff Vanderlip, director, ASIC Technical Marketing, LSI Logic Corporation. "With Physical RTL Optimization, we analyze, identify, and resolve RTL architecture and coding issues that cause layout bottlenecks while the RTL code is being written. This provides substantial improvement in layout predictability and turnaround time." "The RTL analysis LSI Logic performs is very helpful to our design engineers," said Dan Cimino, director of ASIC Development, Extreme Networks, a market leader in broadband Ethernet networking solutions. "Because the analysis is performed fairly early in the design cycle, it allows us to obtain feedback before we complete our first netlist. We believe this improves the quality of our netlists and speeds up our design debug time. Overall, we believe the RTL analysis procedure speeds up the design process, which is a major goal for Extreme." In complex SoC designs, major physical design issues must be resolved in either the chip-level architecture or the RTL architecture and coding. Once RTL is coded, resolving major physical design issues often requires time-consuming iterations. The LSI Logic PRO flow provides a pre-emptive diagnosis on the RTL code, allowing early visibility into issues such as routing congestion and critical-path timing violations created by sub-optimal RTL coding and architecture. "Current-generation tools and flows focus on optimization at the gate level," said Juergen Lahner, manager of LSI Logic's RTL Handover group. "The majority of physical design problems are inherent in RTL coding and architecture, and they are not identifiable once the RTL has been synthesized into a gate-level netlist. Without directly linking timing and congestion problems in physical design to the source of the problem in RTL code, designers are subjected to resolving physical RTL problems through a difficult and lengthy iterative process." LSI Logic targets physical RTL optimization on all of its Gflx 0.11 µm and G90 90 nm designs, as well as the majority of its G12 0.18 µm designs. Expanding the current access of the PRO flow by LSI Logic ASIC customer engineers in the company's design centers worldwide, the LSI Logic PRO flow is now available for use at customer sites. By having the LSI Logic PRO flow readily accessible, customers can be relieved of RTL code confidentiality concerns, and they realize faster design iterations by shortening the learning curve for developing physically optimized RTL code. Customers choosing on-site access will retain full support of LSI Logic ASIC customer engineers who will analyze LSI Logic PRO results and identify major problems in customer design codes within a few days of receiving a report.

LSI Logic, with the use of Tera System's TeraForm-LPA RTL prototyping tool, has developed its physical RTL optimization (PRO) flow, which provides an early look at the physical results of a design, and highlights potential problem areas. The company contends that the focus for design optimization should be on eliminating RTL architectures and coding constructs that cause problems in the physical design. It claims that improvements of 20–40% can be made by optimizing the architecture and coding. LSI studied about 100 design and design variations to arrive a set of 20 rules that are used to analyze the RTL code. The 20 rules are organized in a database that is then linked to the TeraForm-LPA RTL prototyping tool. Additional rules can be added to the database as they are developed. The company then grouped these rules into three categories: timing and congestion, structural, and other rules such as large arithmetic structures. Structural rules include items such as unconstrained I/Os, high-fanout nets, unregistered outputs, and critical MUX structures. The technique developed by LSI is several steps greater in complexity than linting tools. According to the company, linting tools are useful for enforcing checks on coding style, semantics, comments, and re-usability, but are incapable of understanding the impact of the RTL code on gate count, timing, or congestion.

Home    Product of the Week    App Notes    Tech Notes    Newsletters   

		Click here to get your listing up.