Leopard Logic and TSMC Enable Configurable ASICs

The manufacturer says . . .

Murray Disman says . . .

Leopard Logic and TSMC Enable Configurable Silicon Platforms Based on HyperBlox FP Embedded FPGA Cores CUPERTINO and SAN JOSE, Calif.--Nov. 22, 2002--Leopard Logic, Inc., a provider of embedded programmable logic solutions, and Taiwan Semiconductor Manufacturing Company Ltd. (TSMC), the world's largest dedicated semiconductor foundry, announced the availability of Leopard Logic's HyperBlox FP embedded FPGA cores that are process-specific to TSMC's 0.18 µm process technology. HyperBlox FP cores are SRAM-based and do not require any special process options. The layouts are optimized for maximum performance and for robust and reliable operation. Leopard Logic's suite of silicon-proven HyperBlox programmable logic cores enables the creation of configurable System-on-a-Chip (SoC) platforms that can be adapted rapidly to ever-changing application needs simply by generating and downloading new configuration bit streams. The combination of embedded FPGA cores with hard-wired logic functions in a best-of-breed platform provides significant advantages in terms of performance, density, power, and cost over the use of discrete FPGAs. "Leopard Logic's technology enables our customers to keep their designs flexible and to increase the production volume for a given design by leveraging the same design into multiple applications. Embedded FPGA has the potential to become a basic building block of future SoCs, much like embedded memories and processors are today," said Ed Chen, director of design and e-services marketing at TSMC. Seamless integration of the HyperBlox cores with leading design flows and methodologies via industry-standard data-exchange formats is facilitated by Leopard Logic's ToolBlox suite of development tools and design kits. No changes to the traditional ASIC design flow are required to take advantage of this innovative technology. Leopard Logic's embedded FPGA cores are now part of TSMC's IP Alliance Program, which offers the industry's largest catalog of third-party, silicon-verified, production-proven foundry-specific intellectual property. Vendor cores are validated in TSMC silicon to ensure the best possible design experience, easiest design reuse, and the fastest integration into the overall design system. TSMC's "best of class" third-party IP offerings include system-level cores that provide high-performance functions. All cores in the TSMC catalog are created, directly sold, and directly supported by the individual IP vendor to better support each customer's particular design and business model. Each TSMC process-proven IP core complies with TSMC design rules and models. "Partnering with TSMC as the leading independent foundry is a major milestone in Leopard Logic's strategy to proliferate our FPGA cores to fabless and fab-lite semiconductor companies and original equipment manufacturers (OEMs). We see significant customer interest in TSMC's 0.18 and 0.13 µm process technologies, and we are working on the silicon qualification for our 0.13 µm cores," commented Stefan Tamme, Leopard Logic's vice president of sales and marketing.

The idea of embedded SRAM-based FPGA blocks in cell-based ASICs has been kicked around for several years now. The basic concept is good. It was thought that these embedded blocks could be used to correct design errors, adapt a single ASIC for multiple applications, and/or change the design to match evolving standards. The results, however, have not lived up to the expectations. The first attempt was by Adaptive Silicon, who worked with LSI Logic. Their try was followed by Actel, who attempted to sell an SRAM-based FPGA core for ASIC or ASSP use. Leopard Logic was next and then followed by Xilinx and IBM, who announced that they were jointly developing a SRAM-based core for use in IBM's cell-based ASICs. This latest announcement by TSMC and Leopard Logic makes the FPGA core more widely available through TSMC's IP Alliance Program. Leopard's HyperBlox cores will be available for TSMC's 0.18 µm process technology. Leopard is working on a 0.13 µm version of the core for TSMC's 0.13 µm process. Each of the new entrants in this area claims to understand and have corrected the errors made by their predecessors. However, the basic shortcomings of this approach are the relatively large areas required and the slow speed, compared to that of the ASIC, of the FPGA core. In addition, questions about the size of the core, how many cores to use, and the placement of the core need to be answered for each implementation. One hates to be negative about such a promising idea, but the lack of success in this area leads me to have doubts about the entire concept. The idea has been around for several years now and is not that complex. Something good should have happened by now.

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