LSI Introduces First RapidChip Platform

The manufacturer says . . .

Murray Disman says . . .

LSI Logic Introduces First Communications Slice for RapidChip Product Family RapidChip halves time-to-market while reducing costs; lowers design and manufacturing risk for high-performance, high-density custom chips StreamSlice, the first RapidChip offering, features 10-gigabit industry-standard interfaces with 3 million usable gates of customer-configurable logic Attend our RapidChip StreamSlice Web seminar Feb. 27, 2003 MILPITAS, Calif.--Jan. 20, 2003--Delivering on its promise to speed time-to-market and lower barriers to high-performance custom silicon through platform-based design, LSI Logic Corporation introduced StreamSlice, the first offering in its RapidChip configurable product family. Featuring 20 Gbits/s of full-duplex throughput, StreamSlice targets high-end switches, routers, and other communications system applications. "With the RapidChip StreamSlice platform, communications system designers can take advantage of the density, performance, and customization benefits of cell-based ASICs combined with the low development costs and fast time-to-market advantages of FPGAs," said Rick Marz, executive vice president, LSI Logic Communications and ASIC Technology. "The RapidChip approach meets the needs of the growing underserved mid-volume market." A "slice" is a pre-manufactured chip in which all silicon layers have been built, leaving the top five metal layers to be completed with the customer's unique IP. RapidChip devices such as StreamSlice are easily customizable by building on the features already present in the slice, then adding blocks of intellectual property from the LSI Logic CoreWare library along with the customer's unique logic. System designers can use StreamSlice to eliminate interface integration challenges and create custom high-density chips faster, more predictably, and at a lower cost. Multiple sets of embedded high-speed serializers/deserializers (SerDes) enable the use of proven, industry-compliant interfaces including, SPI4.2, XAUI, Gigabit Ethernet, Fibre Channel, and InfiniBand. StreamSlice also offers 3.3 megabits of embedded memory and 3 million usable gates of customer-configurable logic. "The proven, pre-placed high-speed interfaces used in StreamSlice can eliminate from six to nine months of design effort and risk from the development schedule," said Tom Sandoval, vice president of communications marketing, LSI Logic's Communications and ASIC division. "StreamSlice delivers on the LSI Logic RapidChip promise to reduce time-to-market, development cost, and risk." Offering designers the flexibility of using multiple proven standard interfaces, StreamSlice provides a platform for 10 Gbits/s of data-path processing between 16-channel interfaces such as SPI4.2 and 4-channel high-speed interfaces such as XAUI. Individually, these high-speed channels can support the Gigabit Ethernet, Fibre Channel, and InfiniBand standards, or a proprietary interface in the 1.0625–3.2 Gbits/s range. "Customizable standard cell functionality combined with fast, predictable time-to-market is now a reality," said Jerry Worchel, a senior analyst with market research firm In-Stat/MDR. "This first slice in the LSI Logic RapidChip family will serve the emerging middle segment of the communications market that need to quickly create custom designs at a low cost and in the shortest possible time." The first of many RapidChip product slices to be introduced, StreamSlice products are in design today, and are expected to be manufactured in Q1'03 using LSI Logic's G12 (0.18 µm) process technologies at its world-class Gresham, Oregon, manufacturing campus. About RapidChip The RapidChip semiconductor platform combines the high-density, high-performance benefits of cell-based ASICs with the fast time-to-market and customization benefits of FPGAs, and the proven IP benefits of ASSPs. Targeting the communications, consumer and storage markets, RapidChip uses LSI Logic's high-performance field-tested CoreWare IP, customizable logic, embedded memory, and innovative design concepts to significantly reduce design and manufacturing risk and costs. RapidChip also provides a fast and seamless migration path to full standard-cell ASIC—driving unit costs even lower. Unique to RapidChip is the customer-friendly interface that dramatically simplifies the underlying complexity of the design tools and flows associated with SoC design. Rule sets automatically manage architectural design, verification, and physical design. As a result, design schedules for high-performance chips are very predictable. Information on RapidChip technology is available through LSI Logic's direct sales channels and worldwide distribution partners.

RapidChip, first announced by LSI last September, is the company's approach towards circumventing the high design and NRE costs and long development times associated with cell-based ASICs. The basic idea is to provide customers with a silicon platform that contains a substantial amount of application-specific embedded resources and a gate-array section (with a capacity of three to eight million ASIC gates) that can be customized to a user's requirements with four metal layers. The RapidChip platforms can be fabricated up to the final four metal layers, and are then stocked for customer use. This clearly saves a good deal of time to first silicon, and results in reduced NRE mask charges. However, it is not clear as to how much the design and verification effort will be reduced. There are a number of other ASIC offerings that can be customized to a user's design with several metal layers. These are usually called modular arrays, a term introduced by Lightspeed Semiconductor. The makeup of the logic cells or modules is more complex than the basic gates used by LSI Logic. NEC, for example, uses multiplexer-based logic and a register in each cell. Companies that offer modular-array ASICs include AMI Semiconductor, Chip Express, eASIC, Fujitsu Microelectronics, Lightspeed Semiconductor, and NEC Electronics. The HardCopy devices from Altera can be classified as modular arrays, but are only capable of converting designs for Altera FPGAs. AMI is making its XPressArray parts using a 0.18 µm process at TSMC, and customizes its devices with two metal layers that are applied in-house. Chip Express is now using a 0.25 µm process. NEC's first family of modular-array ISSPs (Instant Silicon Solution Platforms) is being produced using the its 0.13 µm UX4 process. This series contains three members with rated logic capacities of 227K, 530K, and 1109K gates. Each of the basic cells contains multiplexer-based logic and a register. The largest part in the series contains some 60K registers. LSI Logic's first RapidChip platform, StreamSlice, contains a variety of embedded I/O configurations that makes the device suitable for high-throughput applications that include telecommunication switchers, routers, and other system functions. According to LSI Logic, chips based on the StreamSlice platform are now being designed and will be produced during 1Q03 using its 0.18 µm G12 process. LSI's StreamSlice has 3 million gates for the users design, 2.6MB of single-port SRAM, 650KB of dual-port SRAM, and an 80-bit wide DDR SDRAM interface. Also embedded in the device are 36 HyperPHY I/Os interfaces that run at speeds from 622 to 832 Mbits/s and 12 GigaBlaze® I/Os that can support data rates ranging from 1.0625 to 3.2 Gbits/s. This announcement covers the first of two StreamSlice products that LSI will introduce this year. Six more communications-oriented StreamSlice platforms are planned for next year. LSI also plans to introduce RapidChip platforms for storage and consumer-oriented applications.

Home    Product of the Week    App Notes    Tech Notes    Newsletters   

		Click here to get your listing up.