Toshiba Launches ASIC Platform

The manufacturer says . . .

Murray Disman says . . .

Toshiba Launches SoCMosaic Custom Chip Platform New Platform Reduces Time-to-Market for Customizable SOCs to 6 Months SAN JOSE, Calif.--Jan. 20, 2003--Toshiba America Electronic Components, Inc. (TAEC) announced the introduction of SoCMosaic custom chip, a new platform-based design approach that can reduce time-to-market for a customizable system-on-a-chip (SoC) to as little as six months. In a companion news release, TAEC announced the ASIC IP Partner Program and disclosed the first participating companies. SoCMosaic custom chip achieves rapid customization of complex SoC designs by using commodity IP blocks, standardized bus interfaces, a scalable bus system, a register-transfer level (RTL) testbench, and high-level, cycle-accurate C simulation. Pre-verified, pre-tested commodity and differentiating IP allows maximum flexibility. "By using a configurable IP platform, pre-verified and pre-tested IP, and support for common bus interfaces, SoCMosaic custom chip can slash total design time from a typical 18 months to as little as four months," said Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC. The turnaround time to get a finished chip to market runs about six months. "Our value proposition includes complete system-level support together with Toshiba's proven high-yield, high-volume advanced process technology. For platform-based SoCs to become pervasive, ASIC vendors must take responsibility for hardware/software integration, and we intend to apply our leadership." System-level support includes hardware and software design (with firmware and middleware) running on cycle-accurate system-level models for the early development of application software. TAEC intends to be active partners with its customers at the system design level, engaging with them early in the design process, and delivering software and silicon with an innovative business model. Mr. Tobias said that he was targeting system companies developing board-level products that were looking to add features to their end products to increase market share or reduce system cost through SoC integration. He explained that many of those companies lacked internal design resources or the specialized skill sets needed for complex SoC design. Likely customers also include system companies temporarily without the means to do yet another chip design project. The SoCMosaic custom chip IP platform supports standard operating systems such as Linux and other real-time operating systems, contains common peripheral functions as commodity IP blocks, including I/O, interrupts, counters, and serial ports plus processor cores. Customers then select differentiating IP such as embedded DRAM, and higher level system interfaces like Ethernet, USB, 1394, PCI controllers, SerDes, and optimized hardware/software application function such as VoIP, MPEG, and 802.11 from Toshiba's IP library. Toshiba also offers a range of analog IP with several variants to each IP block to meet various design requirements, such as high-speed, low-power, small area, or low noise. Toshiba helps the customer implement the product by mapping a functional simulation to the platform, selecting IP from the IP library or obtaining working, verified IP blocks from third parties. Then Toshiba engineers create a testbench to make fast, executable C models of programmable blocks for early software development. Toshiba's software services team works concurrently with hardware development for software driver and API adaptation, RTOS implementation, and standardized middleware solutions. On-chip specialized hardware supports software debugging. The resulting hardware/software working model allows the design to be validated and tested before implementation. Roadmap Over the course of the next year, TAEC is planning to roll out the following with prioritization based on customer demand. An FPGA board to implement the platform with customer IP extensions. This is useful for software validation and hardware environment testing. A second platform that adds DSP to get a RISC/DSP/logic pre-verified multi-master starting point for derivatives design. Software service with API adaptation and RTOS implementation. The inclusion of standardized middleware (i.e., MPEG4, JPEG, MP3, etc.) is possible. An expanded IP library targeting general-purpose IP for networking, multimedia, printer, and storage applications. High-level C models for functional execution of the design before implementation and early software development before the hardware is ready. Platforms are provided as soft RTL code that is synthesizable into any technology, including 0.18 µm, 0.13 µm, 90 nm, or 65 nm. Speed-optimization services will be provided by Toshiba. Availability and Pricing TAEC is accepting a limited number of designs now, and expects to announce general availability of the first SoCMosaic custom chip platform in April, 2003. The V.1 platform is aimed at embedded applications that will combine application-specific support with a single control processor running Linux or an RTOS in low-end networking and consumer applications. Customer sample shipments are expected to begin in the second quarter of 2003. SoCMosaic custom chip platform V.2 will add support for multiple processor cores and high-throughput multimedia and high-end networking systems. V.2 is in development, with availability expected in the second half of 2003.

Toshiba's main emphasis with its SoCMosaic platform is to reduce ASIC design times from 18 months to as little as 6 months. The key to this approach is the use of pre-tested and pre-verified hardware IP blocks, standardized bus interfaces and bus systems, an RTL testbench, and high-level, cycle-accurate C simulation. The approach follows VSIA's mantra concerning the reuse of IP—use it, but don't modify it. One of the more important aspects of the Toshiba's design flow is the use of C, hopefully SystemC, models of all of the IP cores so that rapid simulations of the design can be performed. To meet this requirement, Toshiba has established its ASIC IP Partner Program. The initial members of the program include Denali Software, GDA Technologies, Mentor Graphics, Sonics, and Synopsys. The ASIC IP program roadmap includes the planned addition of digital signal processing and general-purpose IP for networking, multimedia, printers, and storage applications. Toshiba claims that it will impose stringent requirements for quality, test coverage, documentation, and support for all selected IP, and will manage the IP vendor interface for its customers. V.1 of the SoCMosaic platform is aimed at embedded applications that support a single control processor running Linux or an RTOS in low-end networking and consumer applications. The processor used in V.1 is the ARM 926. According to the company, the V.2 SoCMosaic platform will add support for multiple processor cores and high-throughput multimedia and high-end networking systems. V.2 is in development, with availability expected in the second half of 2003. Toshiba has also announced its 1.2V T300 90 nm ASIC family based on its CMOS4 process. The claim by the company is that 11-layer copper wire and low-k dielectric insulating material delivers roughly a 100% increase in gate integration, a 20% increase in gate speed, and a 50% reduction in power consumption compared to the previous-generation 0.13 µm process technology (TC280). Toshiba is offering two types of trench-capacitor embedded DRAM cores for T300 ASIC designs. The SD type is for high-bandwidth applications, and can be clocked at 300 MHz with a maximum data rate of 9.6 Gbits/s. The FA type of DRAM is optimized for fast access. Random access times of 6 to 8 ns are possible. The maximum I/O width to the memory is 288 bits. The company is now doing designs, and claims that samples have been delivered. It expects to be in full production before the end of 2003.

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