Toshiba and Elixent to Develop Reconfigurable SoCs

The manufacturer says . . .

Murray Disman says . . .

Toshiba and Elixent Agree to Jointly Develop Reconfigurable Platform SoCs First platform device to be available in 2003 BRISTOL, England—Jan. 27, 2003--Elixent has entered into an agreement with Toshiba to jointly develop a platform System-on-a-Chip (SoC) that integrates Elixent's D-Fabrix reconfigurable algorithm processing array with Toshiba's MeP configurable processor core. This SoC will be used as a reconfigurable evaluation and development platform by both companies. The D-Fabrix array will be used to accelerate algorithm processing and provide dynamic reconfigurability within the platform. The resulting platform SoC will be useful for the implementation of a broad range of consumer applications, combining the benefits of Toshiba's MeP processor and Elixent's reconfigurable technology. With rapidly rising mask-set costs being incurred because of the move to 90 nm and 65 nm, a different technique is essential for cost-effective production. Elixent's reconfigurable technology will help semiconductor companies maintain their lead on the cutting-edge processes needed to manufacture SoCs at these new geometries. "We evaluated many solutions before choosing Elixent," said Dr Furuyama, General Manager of Toshiba's SoC Research and Development Center. "D-Fabrix is the reconfigurable algorithm processor that will well fit with Toshiba's MeP platform and thus will efficiently provide various benefits." The combination of dynamic reconfiguration and changing the algorithm-processing architecture on-the-fly under the control of Toshiba's MeP processor delivers substantial savings in cost and power. It produces a completely programmable device with performance exceeding that of the fastest DSPs. "We are convinced that this technology will trigger substantial change in the industry," commented Kenn Lamb, Elixent's CEO. "From the earliest development of D-Fabrix, starting over six years ago at HP Labs, it was apparent that the potential cost, speed, and power-consumption benefits would make it a winning solution," he continued. "This announcement shows how right we were, and we are very excited about this agreement with Toshiba." About Elixent's Reconfigurable Algorithm Processing Architecture Elixent's D-Fabrix RAP platform implements algorithms in "Virtual Hardware," allowing the creation of a hardware accelerator for every algorithm in a system. By virtue of reconfigurability, it can implement multiple hardware accelerators in the same silicon area, giving high silicon utilization. Further, this reconfigurability allows functionality to be added or changed post-fabrication, allowing bugs to be fixed, new functions to be added, or even the whole chip to be customized. It achieves this by mapping algorithms to a fine-grained processing array made up of ALUs, registers, and memories, giving it a unique ability to adapt to any algorithm or data-path width. This provides the flexibility of a software solution with the performance of a hard-wired ASIC. Through dynamic reconfiguration, Elixent's D-Fabrix array allows for a high degree of silicon reuse, leading to lower device cost. In benchmarks against standard DSP processors, D-Fabrix provides 10× the performance in less silicon area—and with greatly reduced power consumption. Additionally, D-Fabrix enables a new class of platform devices that can be truly multi-functional—supporting multiple applications and adapting efficiently to changing specifications.

Elixent was founded in October, 2000, in Bristol, England, as a spin-off from Hewlett-Packard's Research Laboratories. The founders of Elixent had worked together at HP for four years, developing the concept of a Reconfigurable Algorithm Processing (RAP) platform. Funding for the venture, with $14 million in backing, was led by the VC firm 3i, with strategic investments from HP and Actel. The basic structure of Elixent's D-Fabrix core is an array of 4-bit ALUs, registers, and blocks of embedded RAM. The ALUs can be cascaded to process 8-, 16-, or 32-bit wide streams. The company estimates that an array with 16 ALUs running at 100 MHz can perform up to 400 million 16-bit operations per second. Toshiba's 32-bit MeP (media embedded processor) RISC processor uses 16- and 32-bit instructions, has 16 general-purpose registers, and a five-stage pipeline. The architecture was introduced in April, 2002, and is aimed at multimedia applications. The interest in the D-Fabrix array technology is for use in accelerating signal-processing algorithms. Elixent demonstrated the capabilities of its D-Fabrix Array at the CEATEC show in Japan with a test chip. It was able to JPEG encode an image using five separate sequential configurations of the same programmable chip. A throughput of 30 million pixels per second was achieved when running at 60 MHz. Toshiba and Elixent plan to combine the MeP core and the D-Fabrix array to create a reconfigurable evaluation platform. The RISC processor can be used for general-purpose processing, while the D-Fabrix array can be used to accelerate algorithms as directed by the processor.

Home    Product of the Week    App Notes    Tech Notes    Newsletters   

		Click here to get your listing up.