Cadence Introduces Incisive Verification Platform

The manufacturer says . . .

Murray Disman says . . .

New Cadence Incisive Verification Platform Compresses overall Verification of Nanometer-Scale Designs by up to 50% Platform is first single-kernel solution with Acceleration-on-Demand SAN JOSE, Calif.--Feb. 24, 2003--Cadence Design Systems, Inc., announced the Cadence Incisive verification platform, the first single-kernel verification platform for nanometer-scale designs that supports a unified verification methodology for the embedded software, control, data-path, and analog/mixed-signal/RF design domains. The new platform's unified methodology helps slash testbench development time, verification run time, and debug time, and can compress the overall verification time by up to 50%. This enables a dramatic improvement in time-to-market for semiconductor customers, and accelerated system design-in of complex ICs for design-chain partners. The Incisive platform provides native support for Verilog, VHDL, SystemC, the SystemC Verification Library, property-specification language PSL/Sugar, algorithm development, and Analog/Mixed Signal (AMS). It includes a unique combination of high-performance capabilities: an extensive transaction-level environment; fast, unified test generation; and Acceleration-on-Demand. Cadence also announced three new products as part of the platform: Incisive, a simulation-based, digital verification solution; Incisive-XLD, a solution for up to 10 engineers that can enable more than 100 times the performance of simulation-based verification; and Incisive-XLD Base, which includes an accelerator/emulator base unit—hardware that delivers a performance improvement of 100 to 10,000 times. The company also said it is extending the Cadence IP Partners Program to support third-party verification IP for the platform. "Fragmentation within projects, between projects, and within design chains has created slow, grossly inefficient verification methodologies," said Rahul Razdan, Cadence corporate vice president and general manager, Systems Verification Group. "Success in developing complex designs and nanometer-scale ICs requires phenomenal verification speed and efficiency. This is made possible only by a unified methodology based on a single-kernel architecture with Acceleration-on-Demand. That's something only the Cadence Incisive platform delivers." Definitive Customer Success "We selected Incisive after evaluating it in both SystemC and multi-language mode with VHDL," said Frank Ghenassia, System and Architecture Design Flows Manager, Central Research and Development at STMicroelectronics. Using SystemC transaction-level modeling, we achieved 1,000 times greater performance than with RTL simulation, enabling our embedded-software teams to validate long before detailed RTL was available. This saved us critical time and reduced risk in our system design cycle. This performance increase, combined with native support of VHDL and SystemC in the new, unified platform, ensures consistent hardware and software validation through a reusable system-level testbench for SystemC and RTL." "AMS Designer, part of the Incisive platform, allows us to verify our next-generation mixed-signal circuits," said Dwayne Sherrard, MS CAD manager of AMI Semiconductor. "By taking advantage of behavioral modeling techniques and by being able to cosimulate our digital and analog blocks, we can take our mixed-signal designs to fabrication with confidence." Acceleration-on-Demand For maximum flexibility and performance, Incisive-XLD delivers Acceleration-on-Demand, which gives design teams the run-time option of using up to 10 seats of Incisive, or up to a million gates of acceleration capacity. The acceleration is hosted on a local or remote multi-user Cadence Palladium accelerator/emulator, which can deliver 100 to 10,000 times the performance of simulation. This capability allows design and verification teams to work interactively during the day and run up to a billion verification cycles overnight. The integrated solution is more efficient than others that rely on standalone or nonintegrated acceleration/emulation technologies. "The Incisive platform's Acceleration-on-Demand capability using Palladium provides unparalleled accessibility, flexibility, and performance for hardware-accelerated verification," said Christopher J. Tice, Cadence senior vice president and general manager, Verification Acceleration Group. "Designers can now access the fastest verification solution in their native environments, while dynamically trading off between simulation and hardware-accelerated verification." "Being able to check image quality at a high resolution as early as possible in the design process is extremely important for graphics applications," said Patrick Scheer, Validation manager at Philips SP3D Chip Design GmbH. "Our complex designs require extremely high performance—beyond what simulation alone can offer. We need a combination of simulation, hardware acceleration, and emulation to verify our designs completely. With Palladium, we were able to easily move design data between NC-Sim software simulation and acceleration, even at the sub-module level. Moving to hardware acceleration with the same transaction-level testbench we used in simulation reduced our turnaround time from five-and-a-half days to six minutes." Unified Verification Methodology The Incisive verification platform supports a unified verification methodology for all design domains: embedded software, control, data path, and analog/mixed-signal/RF. This documented methodology is based on proven technology and techniques. It supports evolutionary migration from existing verification approaches. The unified methodology begins with an architecturally accurate, transaction-level Functional Virtual Prototype (FVP). Transaction-level FVPs can run 100 times or more faster than equivalent RTL, making them ideal for architectural performance analysis, early embedded-software verification, and early system design-in. FVPs also provide a fast, full-chip environment for block-level verification. Within a domain, the unified methodology supports top-down and bottom-up approaches. When block-level verification is complete, FVPs serve as the vehicle for integrating verified blocks and running full-chip implementation-level verification with Acceleration-on-Demand. "It is important for our partners developing ARM core-based SoC designs to visualize and validate the full system very early in the design process," said John Goodenough, Global Methodology manager at ARM. "ARM has been working closely with lead EDA partners, including Cadence, to develop SystemC-based transaction-level interfaces and methodology. These AMBA-compliant transaction interfaces will efficiently support the system-level integration and system-verification needs of developers implementing AMBA technology-based systems." In support of the unified verification methodology, the newly extended Cadence IP Partners Program now includes verification IP providers. The program gives customers access to key verification IP, enabling them to reduce their verification time further. It also supports the industry's broadest range of verification IP technology, and is the only program of its kind to address the complete design flow, from system design to system design-in. Pricing and Availability The Incisive verification platform is available immediately on HP, Sun, IBM, and Linux platforms. Specific operating-system support varies by product. U.S. pricing for a one-year license starts at $27,000 for Cadence Incisive, $200,000 for Incisive-XLD, and $360,000 for Incisive-XLD Base. The platform also includes the Cadence NC family, Cadence SPW, Cadence AMS Designer, and Cadence Palladium. Further information and international pricing are available from local Cadence offices.

The heart of Cadence's unified Incisive top-down verification methodology is the transaction-level-based Functional Virtual Prototype (FVP). According to the company, the creation of transaction models takes a fraction of the time required for RTL descriptions, and the transaction models run about 100 times faster. In fact, the claim is made that the Incisive system and methodology can reduce total verification effort and time by a factor of two—a truly significant reduction in project cost. One slight drawback of the new system is that transaction-level models are recommended for all of the major blocks in the system. This includes processors, previous designs, and third-party IP cores. However, the advantages of this approach can easily outweigh the effort required to produce the models. Benefits listed for the methodology include the availability of an executable specification, the ability to execute architectural trade-off and performance analysis, having a model for the early development of embedded software, a hand-off vehicle to the block-level implementation teams, and having a high-speed vehicle for integrating block-level designs. The Incisive unified verification system starts with a SystemC transaction-level description, and works down to the gate level. Gate-level or full-system verification usually requires FPGA-based prototyping or emulation. The system is built around a single kernel from the company's NC simulator. The kernel is claimed to provide native support for Verilog/VHDL, SystemC, Verilog-AMS/VHDL-AMS, and PSL Sugar assertions.

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