ASIC Main | Archives

With chip complexities now routinely exceeding a million gates, and often including third party intellectual property (IP) cores, multiple embedded memories, and multiple clock domains, the requirements for design for test (DFT) and built-in self-test (BIST) are increasingly important. Figure 1 illustrates a typical chip design with what might be called "test engineer's nirvana" -- complete DFT, BIST, scan and boundary scan implementation with a shared IEEE-Std-1149.1/4 test access port controller.

Figure 1 -- A typical complex multimillion gate ASIC design with cores, embedded memories and application specific logic.

Starting with the core, there are several options available for DFT/BIST implementation. Whether the core is purchased from a third party supplier or designed in-house, it needs to contain certain structures to facilitate its testing as part of the complete system-on-chip (SoC) entity. This can be done by providing for either isolation, scan access, or complete BIST control.

With isolation, the core is basically surrounded by a boundary scan chain that can be used to reapply the functional test vectors used to initially test the core design itself when it was in isolation. The main advantage to this method is the resusability of the initially developed test vectors. The disadvantage of this method is that serializing the previously parallel test vectors for application through the core boundary scan chain can result in long test vector sets (and thus longer than desired manufacturing test times for the complete chip).

With scan access, the core is designed to include scan chains that render it completely testable. These scan chains can be accessed via the boundary scan capability, if included, or via multiplexing the core pins with complete chip I/O pads. The tradeoffs here are extra gate delays, the need to make sure that the complete chip has enough I/O pads to handle all of the core I/O signals, and test vector lengths. Multiplexing results in fewer vectors, while using the boundary scan chain to serially apply serial scan vectors can make the number of clock cycles needed to apply all of the scan test vectors to the core unacceptable.

A better approach is to make the core self-testable with a combination of scan and BIST. Scan is often necessary to get the level of fault coverage of the core to an acceptable (e.g., 98-99+%) level, even with BIST techniques. The BIST circuitry will typically consist of a controller, a pattern generator and a multiple input signature analyzer. With this approach, core testing can be accomplished simply by commanding the core BIST controller to initiate self test and knowing what the correct result should be. Testing "at speed" is also possible with the right BIST implementation.

Embedded memories present another challenge. If they are small (e.g., less than about 16K bits), they can typically be tested on-chip by either multiplexing their address and data lines to external SoC I/O pads -- as described above for scan access for the core -- or by using the core processor to apply enough read/write patterns of various types (e.g., C+, C-, March, Moving Inversion March, etc.) to insure the integrity of the memory. This technique, however, often becomes unwieldy when the embedded memories are large, and when there are multiple embedded memory cells. In this situation, it is best to provide each embedded memory cell with its own BIST circuitry (control, address and data generator, and output comparator) and, in the case of multiple embedded memories, a shared memory BIST controller (also as illustrated in Figure 1) to minimize the silicon overhead attributable to the BIST circuitry.

Electronic design automation (EDA) tools exist to automate the process of inserting the necessary scan and BIST structures into the cores and around the embedded memories, and to tie the internal DFT/BIST signals together for effective complete chip testing. These tools can also extract scan/BIST information from cores purchased from third parties so that the BIST or test vectors supplied by the designers of the core can be reused at the full chip level. Thus it is important, if buying cores or embedded memories from third parties, to make sure that the DFT/BIST information is supplied with the core or memory circuitry, and that it is indeed reusable.

Achieving acceptably high fault coverage for the application specific logic on an SoC ASIC -- the "value added" by the SoC design team -- often requires the inclusion of full, almost full or partial scan structures in that logic. With most designs done in either Verilog or VHDL, and then synthesized with logic synthesis EDA tools, it is fairly easy to construct designs that will prevent the effective application of automatic test pattern generation (ATPG) tools, even with the inclusion of scan structures. If asynchronous set/reset circuits, internally generated or gated clock circuits and multiple sequential registers without initialization control -- to name a few -- are included in the design, they can cripple any ATPG tool.

It is thus important to perform a testability analysis of the design's application specific logic. While this can be done at the gate level -- after logic synthesis -- it is much more effective from a time-to-market standpoint to perform this analysis at the RT level prior to logic synthesis. Then, after logic synthesis, a gate level analysis can be performed to double check for any remaining testability problems. Scan synthesis tools are then applied to insert, order, and stitch the required scan chains together. Some of these tools can make use of physical placement information (e.g., def or pdef files) to minimize the routing overhead for the scan chains, and a few of them can automatically repair any testability problems remaining after logic synthesis.

Where an SoC design includes analog or mixed analog/digital circuitry, the DFT/BIST solutions are not quite as advanced as they are for digital-only circuits. The keys to good testability of mixed signal circuits are isolation via something like the IEEE-Std-1149.4 mixed signal testability bus approach -- one that is compatible with the IEEE-Std-1149.1 test access port controller -- and as much analog BIST circuitry as can be accommodated in the silicon. Interestingly enough, large SoC designs are much more often limited by I/O pad constraints than by silicon area, so including BIST structures may actually come "for free" from the silicon overhead standpoint.

Finally, since the chip will undoubtedly by placed in a "next assembly," -- a printed circuit board assembly, multi-chip module, or other final product physical package -- it is important to include boundary scan capability for the overall chip to facilitate its independent testing at the full product level. Ideally, EDA tools will be used to synthesize the boundary scan chain and test access port controller, and to generate the boundary scan description language (BSDL) file needed by the chip's end user. Tools can reduce the time required for these tasks from weeks to only hours.

Figure 2 illustrates the typical sequence of events for implementing DFT and BIST structures into an SoC design.

Figure 2 -- An optimal vertically integrated DFT/BIST strategy design flow

The kind of flow illustrated in Figure 2 can be included in virtually any customized design environment. The key is to select the right point tools for each task, and to integrate them at the appropriate points in the overall design flow. The early inclusion of DFT/BIST considerations, and the acquisition of the tools necessary to automate the testability analysis, scan synthesis, automatic test pattern generation and fault simulation tasks, are just as important for time-to-market and high device quality as are logic synthesis, place and route, parasitic extraction, and static timing analysis.