INTRODUCTION - FPGAs vs. ASICs

In the recent years, FPGA prices have dropped. A 50,000 usable gate FPGA that cost several hundred dollars a few years ago now sells in volume for about $50. Because of their decreasing prices, higher densities, short design cycles, and flexibility, FPGAs are increasingly displacing masked-ASICs particularly in designs with gate counts of 50,000 or less and production volumes of less than 50,000 per year. The very large minimum orders and very high NRE charges associated with masked-ASICs have made them too expensive to develop for all but the highest volume designs. FPGAs are no longer used solely for design prototypes and early production runs. Fewer designs are being converted to masked-ASICs. More and more frequently, FPGAs are being used for production manufacturing.

This does not mean that FPGAs are cheap relative to ASICs. Quite the contrary! When process technologies shrink, they also shrink for ASICs. FPGA programmability relies on hundreds of thousands of transistors that are not required for non-programmable devices. At any process technology a masked-ASIC will always have a substantially smaller die size and unit pricing that is 75% to 80% lower than that of a comparable FPGA. As a result, for designs with sufficient volume to offset the development costs, an ASIC will always be the most cost-effective solution. In fact, extremely cost sensitive consumer applications never use FPGAs, even for early generations. These designs are typically implemented directly in a masked-ASIC. These cost sensitive designs are robbed of the flexibility and quick product development cycles afforded by a programmable solution.

The other low to intermediate volume designs that cannot support the NRE and long lead times associated with masked ASICs go to production in FPGAs. These designs benefit from quick and flexible prototyping and the ability to implement competitive product enhancements as soon as they are designed. However, the only cost reduction path for these designs has been to wait until the next manufacturing process lithography shrink brings down FPGA prices.

Clear Logic has developed a solution for both FPGA and ASIC designs. The company's new CL10KA family of Vertical-Link-configured ASICS provides low-cost, no NRE ASICs. They are prototyped by using Altera FLEX 10KA FPGAs. Clear Logic configures them by using the prototype bitstream. Cost sensitive designs that previously could only be implemented in a conventional gate array, can now be prototyped using Altera's popular FLEX 10KA FPGAs and immediately qualified for production using Clear Logic's CL10KA ASICs.

Since CL10KA prototypes are done using programmable FPGA, prototypes are available immediately and multiple design iterations can be done with no risk or expense. The FPGA prototyping medium is an off-the-shelf part, avoiding the expensive mask-charges and six to eight week lead times associated with getting ASIC prototypes from other ASIC vendors. Samples for qualification are available within two weeks and production quantities are available within six weeks - _ to 1/3 the turn-around for other ASICs. ASIC designers now have the flexibility, short design cycle and quick turn-around provided by a programmable solution, with the low cost, low power and design security of a masked-ASIC.

CLEAR LOGIC HISTORY - LASIC AND LPLD TECHNOLOGIES

In 1997, Clear Logic developed its proprietary Laser-configured ASIC (LASIC) technology. The LASIC technology made it possible to convert Altera FPGAs to a low-cost ASIC-type solution without any customer-side engineering, NRE charges, test vector generation or minimum order quantities. Since the LASIC technology utilizes a device architecture that corresponds to that of the Altera user-programmable device, it will directly accept unmodified Altera bit streams, thereby eliminating the complete re-design usually associated with ASIC conversion. Clear Logic's internal bitstream extraction tools convert Altera bitstreams to laser configuration instructions and automatically generate test vectors with 100% fault coverage.

The company's Clear Fire laser configuration technology uses these instructions to individually configure each die on the wafer in a few seconds, thereby eliminating mask charges and minimum order quantities associated with gate- arrays. In addition, prototypes are available within two weeks and production quantities are available within four weeks. Since Clear Logic devices are pin-compatible with their Altera counterparts, there is no need to redesign the printed circuit board. In fact Clear Logic devices are interchangeable in the same socket with their corresponding Altera FPGAs and CPLDs.

Smaller Die Sizes, Lower Prices -- Clear Logic devices are not programmable and therefore do not require the thousands of transistors associated with FPGA and CPLD programmability. By eliminating hundreds of thousands of transistors, Clear Logic achieved die sizes for comparable density products that are 30% to 50% smaller than Altera's and can price its devices 30% to 70% lower than Altera.

Low-cost Replacements for Multiple Altera Programmable Families -- In 1998, Clear Logic introduced the CL8000 family that replaces Altera's FLEX 8000 family of FPGAs. In 1999, Clear Logic introduced its CL7000 family of replacements for MAX 7000 and MAX 7000A CPLDs. Since the first Clear Logic devices were introduced Clear Logic has successfully converted over 350 customer designs. All 350 designs have worked in the Altera socket the first time.

CL8000 Laser-configured ASICs (LASICs) -- CL8000 LASICs are architecturally compatible with Altera's FLEX 8000 family. In both devices the logic elements are grouped together in coarse- grained blocks. Clear Logic calls these blocks Logic Building Blocks (LBB). Each LBB contains multiple logic elements that are directly connected to each other. High-speed interconnect on CL8000 devices serves a similar function to Altera's FastTrack .

Each FLEX 8000 logic element consists of a programmable four input look-up table (LUT), a register, high-speed cascade and carry-chain logic, and configuration elements. Clear Logic's CL8000 logic elements consist of a laser-configurable four input look-up table (LUT), a register, cascade and carry-chain logic. Like all FPGAs, the FLEX 8000 architecture is routing intensive. Any logic element can be connected to any other logic element regardless of its location in the logic array. Each FLEX 8000 configuration element requires six transistors with the result that FLEX 8000 routing resources can take up as much a 50% of the FLEX 8000 die.

In its CL8000 family of LASIC replacement for FLEX 8000 FPGAs, Clear Logic replaced all six FLEX 8000 configuration element transistors with a single horizontal metal link, radically reducing the amount of silicon required for the same functionality. The FPGA bitstream can be implemented directly in the corresponding LASIC without resorting to VHDL, logic synthesis or other complex and unreliable conversion techniques. There is no customer involvement. By replacing large configuration transistors with metal links that draw no power, Clear Logic reduced power consumption and die size by as much as 30% from those of Altera FLEX 8000 FPGAs.

CL7000 Laser-Processed Logic Devices (LPLDs) -- In the MAX 7000 CPLD family, logic is performed by macrocells and product term AND arrays that are connected by a programmable interconnect array (PIA). Each connection point in the MAX 7000 PIA has eleven transistors. When developing its CL7000 Laser Processed Logic Device (LPLD) replacements for MAX 7000 CPLDs, Clear Logic replaced all eleven of these transistors with a single metal link that draws no power, thereby reducing the PIA silicon by 72%. The metal link has lower resistance and capacitance than a transistor, so CL7000 devices are faster and draw less power than Altera MAX 7000 CPLDs.

Clear Logic also reduced the silicon required for the AND array inputs. Six transistors are used to configure the AND array input term (three for each of the two word lines). All six of the transistors are required to support all of the combinations that could result from a customer design, so their number cannot be reduced in a programmable device.

Since Clear Logic LPLDS are not customer-programmable, the company has been able to replace these six transistors in the Altera MAX 7000 architecture with just three metal links and a single transistor. The exact configuration of each input term and its inversion, or lack thereof, are taken from the Altera MAX 7K bitstream and implemented in the laser-configuration so that one link controls disabling of the input term. By eliminating five of the six transistors in the MAX 7000 AND array-input term, Clear Logic has reduced the silicon required to implement the product term AND array by 55%. The lower bit line capacitance further improves the speed and power consumption characteristics of the device and increases noise immunity.

Since CL7000 devices are not programmable, there is no programming control circuitry, resulting in further die size savings. Altogether, Clear Logic eliminates more than a million transistors from the MAX 7512AE architecture and achieves a 40% die size reduction.

In both the FLEX 8000 and the MAX 7000 architectures, the dramatic reduction in die size has allowed Clear Logic to price its replacement parts at a substantial discount from comparable Altera CPLDs and FPGAs. In addition, Clear Logic replacements for Altera programmable devices consume less power and have faster delays.

CLEAR-LOGIC'S NEWEST CL10KA ASICs HAVE AN FPGA-BASED DESIGN FLOW

Clear Logic is introducing its newest no-NRE, quick turn-around ASICs that are prototyped using programmable logic that has identical functionality, including internal timing relationships, pin-out and electrical I/O characteristics. Initially available in densities of 30,000 to 100,000 gates, Clear Logic's CL10KA ASIC family has coarse-grained blocks of logic, called logic building blocks or LBBs each of which has eight logic elements. Each logic element contains a four-input look-up table (LUT), a programmable register with local clock enable control, an output structure that supports sequential or combinatorial outputs, and configuration elements for routing. CL10KA ASICs also have discrete embedded SRAM arrays, called embedded SRAM blocks or ESBs with 2Kbits of SRAM each. High-speed buses connect the CL10KA LBBs to each other.

Altera's FLEX 10KA FPGAs can be used to prototype CL10KA ASICs because they contain the same functionality, including logic elements with a four-input look-up table capable of sequential or combinatorial logic that are arranged in Logic Building Blocks (LBBs) of eight directly connected logic elements each connected by interconnect. FLEX 10KA devices also have a 2Kbit embedded array block (EAB) for every eight logic elements. The two device families both have pin-outs and I/O loading that are identical. In fact, the FLEX 10KA bitstream generated during CL10KA prototype process is used to directly configure the CL10KA ASIC without modification. Once the FPGA-based prototype design is done, customers need only send the prototype bitstream to Clear Logic. They will receive CL10KA sample parts for production qualification within two weeks. The Clear Logic ASIC is guaranteed to work identically to the Altera FLEX 10KA prototype in the same socket.

The only differences between Clear Logic's CL10KA ASICs and the FLEX 10KA prototyping medium is that the Altera FPGAs require up to six configuration transistors for every logic configuration element for programmability. These transistors take up much more silicon, resulting in a die size that is two and one-half times larger than that of the CL10KA ASIC, consumes more power and costs four times as much. Because only a few units are required to debug a new design, the FLEX 10KA is an ideal prototyping vehicle for the Clear Logic ASIC.

SECOND GENERATION LINK-CONFIGURATION TECHNOLOGY

In developing its CL10KA family, Clear Logic has evolved its original Laser-configured ASIC (LASIC) technology to a second generation Vertical Link-configured ASIC (V-LASIC) technology that provides even better silicon efficiency. Clear Logic replaced the laser-configured horizontal links of the original Clear Logic ASIC technology with vertical links for a new vertical link- configured ASIC architecture.

Silicon Requirements for Laser Configured Links - In order to ensure that metal lines are not melted by the high powered lasers used to cut the links, the horizontal links on Clear Logic's CL8000 devices are each 7 microns in length. Seven microns is sufficient length to dissipate the heat generated during laser configuration. Horizontal links also must be spaced 3.5 microns apart to prevent neighboring links from being inadvertently blown, during device configuration. In addition, no circuitry can be underneath a laser link, because the laser would destroy the circuitry when cutting the link. Thus, in spite of the fact that Clear Logic's laser-configured horizontal link technology saves a substantial area of silicon, quite a bit of silicon is needed to accommodate high energy lasers. Even with these restrictions, a single horizontal laser link replaces multiple transistors required in programmable devices and results in die sizes that are 30% smaller than those of programmable products.

Vertical Link Technology - Clear Logic's researchers determined that a substantial amount of die area could be conserved by replacing horizontal laser links with vertical links though the vias between the various metal layers on CL10KA devices. Vias have been used for years to connect the various metal layers on multi-layered integrated circuits. In the Link-Configured ASIC technology, many more vias are created than would be the case in an ordinary multi-layered IC. These vias are filled with plugs creating the vertical links that replace horizontal links in the original ASIC technology. Each vertical link requires only 2.50m2 silicon area -- 96% less than the 54.3m2 required for Clear Logic's previous horizontal link. Using a plug requires no change in the manufacturing process because it is a proven, existing technology. Compared to the area required for an Altera FLEX 10KA configuration element, Clear Logic links use virtually no silicon area.

Laser Configuration - Clear Logic has developed a new technology, which it is in the process of patenting, to create the plugs in the links. The technology allows the links to be disconnected using a low-power laser cutting process. Using the laser is very fast, so devices can be delivered quickly and as first article samples or for volume production. In addition, the new technology allows a much lower energy laser to be used to disconnect the link.

Lower Energy Requirements Further Increase Die Area Savings - The lower energy required to sever the vertical links generates very little heat, therefore providing three additional silicon area efficiencies to CL10KA ASICs. Since vertical links do not have to dissipate as much heat as the horizontal laser- configured links;

1) they do not need to be as long as a horizontal link;
2) they do not have to be placed as far apart as horizontal links; and
3) circuitry can be placed in the area near and underneath the vertical links because the low energy laser will not damage them.

The result of the Vertical-Link-Configured ASIC technology is that the die size reduction is substantially greater than the difference between the sizes of the horizontal link and the vertical link. For example, as shown at right, an AND array input term requires 197 Fm2 of die area using horizontal links, while the same circuit can be implemented in just 48 Fm2 using the vertical links. The Vertical Link-Configured ASIC technology allows circuits to be implemented in of the silicon required by Clear Logic's earlier technology.

60% Smaller Die Size, ASIC Level Prices -- One might expect the embedded SRAM in the CL10KA to limit Clear Logic's die size advantage because there is no way to achieve the type silicon area improvements in the SRAM that Clear Logic can effect in the logic array. However, Clear Logic's development of vertical links has reduced the silicon area required for the logic array by 79%, such that, even with the embedded SRAM, Clear Logic has a 60% smaller overall die size.

The substantially smaller size of the die and improvements in the manufacturing process allow Clear Logic to offer volume pricing for its CL10K50V ASIC as low as $12.95 (for orders as low as 1,000 units) 75% less than the current market price of Altera's FLEX 10K50V FPGA.

DESIGN IMPLEMENTATION

CL10KA ASIC designs are done using Altera FLEX 10KA FPGAs. The design tools are used exactly as they would be for any standard FPGA design. CL10KA designers can use third party intellectual property (IP) cores that have been optimized for the FLEX 10KA architecture. These IP cores will function identically in the CL10KA architecture.

Since Altera FLEX 10KA FPGAs are in-system programmable, designers can quickly prototype and test designs without incurring the costs associated with ASIC prototyping. Multiple design iterations can be done in a day. Since there are no mask charges, designers can be creative, trying new approaches because there is no cost associated with a design error. Also, CL10KA prototypes are available immediately. They do not require a six to eight week fabrication cycle as do other ASICS.

Once the design is done, the customer provides an Altera prototype bitstream file by Internet to Clear Logic. Within two weeks, Clear Logic provides sample CL10KA ASICs for qualification. FAEs are not required to design CL10KA ASICs and customer design confidentiality is maintained because the HDL description remains in the hands of the customer.

Clear Logic uses its ClearShot bitstream extraction tools to generate C L10KA link-configuration data, including complete routing and placement information, from the FLEX 10KA prototype bitstream. The CL10KA ASIC internal timing relationships and device functionality will be identical to those of the FLEX 10KA prototype.

Clear Logic then uses its NoFault software to generate test vectors that are customized to the customer's logic design and provide 100% fault coverage. Customer engineers are completely relieved of the burden of generating test vectors a major task with conventional ASICs.

The entire process, from programmable prototype through qualification samples takes only two weeks. Volume production is available in four to six weeks - _ to 1/3 of the time required by other ASIC vendors. Clear Logic ASIC orders can be canceled as late as 30 days prior to delivery.

BENEFITS TO CURRENT ALTERA FLEX 10KA USERS

FPGAs are expensive. Even with sub-micron process technologies, they cost 400% to 500% more than masked gate arrays. Unfortunately, designs with short product life cycles and low to medium volumes cannot use gate arrays as a realistic cost reduction path.

Clear Logic ASIC devices offer low to medium volume and short product life-cycle designs the low cost and power consumption of a general purpose ASIC, with the ease, flexibility and zero-NRE charges of an FPGA. FLEX 10KA FPGAs can be used for the initial design, prototyping and even early production in high valued-added products. Then it can be migrated effortlessly to an identically functional, but much less expensive CL10KA ASIC.

BENEFITS FOR COST-SENSITIVE ASIC DESIGNERS

Clear Logic offers a new, more flexible design methodology for designers that, because of cost pressures, have historically done their initial design in a masked ASIC. These designers can prototype in a FLEX 10KA FPGA, performing complete design iterations in days instead of months. When they are ready to go into production, they can migrate immediately to a low-cost CL10KA ASIC.