HW/SW coverification is focused on one of the most critical steps of embedded system design, integration of hardware and software. Until recently, this important step was performed in a lab environment by constructing a hardware prototype and running the embedded system software. Debugging was done using equipment such as in-circuit emulators (ICE), logic analyzers, and oscilloscopes. Debugging prototypes late in the design cycle, when the pressure of the project schedule is the greatest, is a tedious, risky, and stressful task. This article is an introduction to the concepts and benefits of HW/SW coverification.

Introduction to Coverification

To solve the problems associated with debugging prototypes in the lab, hardware engineers turned to logic simulation to verify the hardware design before building prototypes. Logic simulators provided a much easier way to observe and correct design errors. Today, Verilog HDL and VHDL are the two industry standard languages for simulating new chips and boards. Even though logic simulation turned out to be much easier than debugging prototypes, hardware engineers still struggled to incorporate the software into these logic simulations. Full-functional models of microprocessors were hard to find, and if they were available as Verilog or VHDL they were too slow to run much software. Consequently, hardware engineers turned to bus functional models and used testbenches to verify the hardware. The testbench became an estimation of which sequences of bus transactions would be caused by software.

Software engineers also turned to simulation to address the problems of debugging in the lab. Instruction set simulators (ISS) and real time operating system (RTOS) simulators were developed to allow software to be debugged on a workstation using source level debuggers. The drawback of these software simulation tools was the lack of a simulation model for the custom hardware. Without an accurate model of the design's custom hardware only the hardware independent levels of software could be simulated.

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