Even though there is a current push to automate and mechanize design reuse, large complex designs still evolve, almost organically, from the digital soup of those that came before. While some useful IP standards are emerging and EDA vendors are making a lot of noise about the reuse capabilities of nearly every tool, the fact remains that design reuse and IP integration are by and large ad-hoc opportunities, not highly-refined processes.

Most design elements being reused today have not been designed specifically for the purpose. These elements are mostly parts and pieces of older designs adopted by the current design team for reasons of expediency. Sometimes they are commercial offerings that must be customized to the task at hand. Often the make/reuse/buy decision is a close call because incorporating an existing design element might be nearly as difficult as designing from scratch.

System-on-Chip designs are composed of logic that span new code, reused components, and intellectual property purchased from others. Debugging these designs requires understanding all the parts and how they work together. A debugging system helps engineers understand complex and unfamiliar logic by letting them rapidly trace and visualize the cause and effect relationships so they can more easily locate and isolate the reasons for bugs.

Understanding is the Key

To reuse a design, the engineers must understand it. Even designs that are specifically sold for reuse are not documented adequately. Most times, designers are forced to reverse-engineer the operation of the part that want to reuse. Moreover, when they incorporate the part with the other elements of their design, they must verify that the resulting combination behaves as expected.

Verification of complex behavior is difficult enough when the engineers are familiar with all of the logic. Reuse and IP make the problem worse by turning some of the boxes black. Black-box verification is extremely difficult, if not impossible. Whenever unexpected behavior is spotted, the symptom must be traced through the design to its source. When that behavior spans more than one block in a design, debugging becomes more difficult. When the behavior involves blocks not designed by the engineer doing the debug, the difficulty, time, and cost of debug increase rapidly.

Determining the cause of erroneous behavior is a grueling process that involves examining many parts of the design, comprehending how they contribute to the observed behavior, eliminating those that are operating correctly, isolating those that are not, and understanding why. Several levels of hierarchy, dozens of files, hundreds of signals, and thousands of lines of code may be involved. Cutting through this maze is essential to rapid debug of functional problems in large complex designs.

Contributing to the difficulty of debugging is the fact that verification of today's designs requires many different tools. Each tool uses its own representation of the design for analysis. But when users try to understand the results of the analysis and debug the problem, they are faced with inconsistent design viewers and commands.

Debugging System

A debugging system such as the Debussy system from Novas Software can help designers combat these complications and contain debug costs. The architecture and use model of such a system make it a universal platform for debugging the results from many verification and analysis tools. Its features, which include tracing, visualization, and automatic debugging, provide the means to understand designs and quickly locate and isolate the part of the design responsible for unexpected behavior. This makes a debugging system an essential element in the design flow when design reuse and IP are involved.

Understanding an unfamiliar design starts with tracing the connectivity and structure of a design through its hierarchy and its source code. Engineers need easy ways to traverse the hierarchy and immediately see the source for any part of the design, then trace drivers and loads by means of simple point-and-click and drag-and-drop operations. Visualization of the design and annotation of simulation results directly on the source view and in the graphical representations take engineers another step toward thorough comprehension of design behavior.

Annotation of makes it easier to understand how each line of the code, bus, and signal is contributing to the design's behavior. Linking these to the waveform viewer and to an efficient database that stores signal value changes over the course of simulation time is essential to provide rapid traversal of the results in the context of the design.

Having a single view of the design across multiple verification tools is very important to maximize debug efficiency. To accomplish this a debugging system compiles the original source files, giving uses a clear view of the design that is not affected by the processing of any particular verification tool.

Comprehending how a design works means understanding how its functional elements relate to each other. The debugging system's visualization tools are critical to design reuse because they reveal interactions that may be quite obscure in unfamiliar designs, even with excellent access to the source. This is because the assignments that contribute to the value of a bus or signal may be spread throughout many different source files. Automatically generating these views across the hierarchy accelerates debugging because it eliminates the tedious manual process of text searching and pencil sketching.

The generated views include traditional nested-block hierarchy views and structural cell-level schematics, state machine bubble diagrams, advanced RTL functional schematics, and unique partial schematics. RTL schematics and state machine views help a user to reverse-engineer unfamiliar HDL code by showing how the parts of a source description relate to each other. Partial schematics are particularly important to cutting through complex logic, for example in a large gate-level design, because they cut away all the extra logic that is not contributing to a problem.

These views are fully integrated with each other and with a fast, compact database for dynamic signal data. This allows users to drag and drop signals between views to rapidly change what they're looking at, twisting and turning their view of the design to help them see what's wrong, and to annotate the verification results on the various views, so they can be observed in the context of the design.

With the right information stored in its database, a debugging system can also automate many costly debug steps. For example, the system analyzes simulation results and the design's logic to determine which of many potential drivers is causing the value of a signal at a particular time. These automatic debugging features also include analysis of bus contention and isolation of the causes of unknown values.

User View

Vweb Corporation develops complex system-on-chip devices to enable digital video on the world wide web. These designs, which implement digital video compression and distribution technologies, both incorporate IP and will themselves be reused by system designers. Vweb's MPEG encoder design demonstrates the difficulty that engineers face today. This design combines outside IP for interfaces such as PCI, Firewire, and two RISC processors with an intensively designed high-performance custom engine consisting of 22 separate state machines and over 20 memories.

Use of the Debussy debugging system accelerated Vweb's design and verification process by making it easier for their designers to understand code written by other engineers. For example, Vweb's engineers use Debussy to trace logic through the design source code so they can better understand the flow of signals and find the relevant drivers for a particular signal transition. They use the system's annotation features to see the value transitions in the context of the source code, and they use its visualization tools to create symbolic logic diagrams from RTL code so they can see the logic flow without wading through the source code. Vweb finds that these capabilities cut the time it takes to design-in IP and verify that it works in the system.

Conclusions

IP integration and design reuse save design time, but they increase the debug burden because they add lots of unfamiliar logic to a design. Users often find that they must effectively reverse engineer this code in order to optimize their designs and verify that the reused components work correctly in context.

Use of a debugging system has been shown to cut debug time and costs by a significant margin, particularly in large complex designs where the engineers are debugging other people's code. Many users estimate savings of 30 to 50 percent.

These savings are particularly important because debugging is an interactive process that carries enormous opportunity costs. Because engineers cannot add new chip value while they are debugging old problems, it is essential for design and verification engineers to have better ways to understand complex and unfamiliar designs so they can resolve design defects as quickly as possible and get back to adding chip features and improving design performance.

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