The growing complexity of ASICs and programmable parts means functional verification is the nightmare that keeps mangers up at night. Designers are creating ASICs that can't be completely verified in a reasonable time with the tools and computing resources they have available. As a result of the gap between what can be designed and what can be verified, achieving a functionally stable design is difficult and involves many iterations.

This paper presents Solidification, a new low-risk methodology for faster debug of ASICs and programmable parts that significantly reduces verification time and effort while increasing quality and robustness of designs.

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