Overview

The eASICore™ is a high performance configurable logic core aimed at accelerating the development cycle and supporting derivatives for System-on-Chip (SoC) products. The eASICore™ architecture is based on the eASIC™ proprietary technology that provides an efficient solution for embedding configurable logic blocks in a fast, easy to implement and cost effective method.

The need for a solution of this type is becoming crucial, as the cost of semiconductor tooling is increasing dramatically with the introduction of smaller process geometries. Moreover, with todayıs complex electronics design, multiple iterations are often required for either fixing bugs or creating design revisions and derivatives. In this reality, both the time-to-market and the NRE spending objectives are becoming a greater challenge to achieve.

Taking into consideration these technology trends, the eASICore™ was developed to allows rapid response to market and spec changes and thus help gaining competitive advantage. The eASICore™ introduces an efficient approach to significantly shorten the SoC or SLI (System Level Integration) development cycle through fast and low cost iterations. By means of its unique technology and architecture, this configurable embedded core provides designers with a flexible and friendly design environment together with the means to get to market first.

The eASIC™ Technology

The eASIC™ technology development is driven by a breakthrough concept of combining an SRAM Look-Up-Table (LUT) cell with metal mask programmable interconnection. The LUT as the dominant logic building block in FPGA is employed together with mask programmability that is the conventional method in Gate Array and Standard Cell. Coupling this innovative concept with efficient implementation led to the development of a configurable logic core that delivers close to Standard Cell performance and density together with FPGA time-to-market and ease of design.

One major issue that drove the need for an alternative solution is the huge silicon area that the existing FPGA devices require for programmable routing. SRAM programmable routing uses diffusion area for every routing segment and thus wasting costly silicon.

Additionally, the immediate impact of the SRAM programmable routing is a huge resistance added by the pass transistors, resulting in high propagation delay. Furthermore, the capacitive load issue carries on the limitation of currently used programmable devices. In the deep sub-micron era, wires get closer, resulting in higher capacitive load, while transistors size decreases and their drive is reduced accordingly. This negative effect is intensified when connection is done through pass transistors controlled by SRAM cells.

The problem is getting even worse as the industry moves to smaller feature size and increased number of gates. Doubling the gate count requires proportionally more area dedicated to routing. Therefore, a larger silicon area is wasted.

The addition of metal layers is one approach the semiconductor industry adopted to cope with this problem. But for FPGAs this solution has a major overhead. In order to program the additional layers, more diffusion resources are required and inevitable routing blocking results from connecting the top layers to the transistors at the diffusion area. This effect conflicts with the added value derived from additional metal layers.

The eASIC™ technology addressed those issues with an innovative embedded configurable logic solution. The eASIC™ technology takes advantage of the already proved successful Look- Up- Table approach for logic implementation, while avoiding the deficiencies of SRAM programmable routing. This is made possible since the routing of the eASICore is performed through metal-to-metal interconnection. The eASIC mask programmable routing, which is done on top of the logic, enables utilizing smaller silicon area and thus reducing the production cost. Additionally, the RC of the eASICore routing is significantly (10 to 100 times) lower compared to SRAM controlled pass transistor devices and therefore the eASICore can offer performance similar to Standard Cell.

The eASICore™ Features

The eASICore™ can be ported across conventional silicon fabrication processes and therefore is flexible for use at various target foundries. The basic eASICore™ was implemented and tested 0.18ım, 6 metal-layer process, obtaining performance and power consumption close to Standard Cell.

• 0.18µm, 6 metal process
• Configuration:
  • All logic is fully configurable with the top two metal layers only
  • Configurable as Dual Port SRAM at 40K bit/mm_ (up to eight 256x16)
  • RAM can be placed anywhere and at any size
  • The wiring is fixed on the silicon but the LUTs can be reprogrammed for limited logic edits to help in debug
• Size: the eASICore is 0.9mm2 with 25K gate equivalence
• High logic density of ~30,000gate/mm_
• As low as 7 day customization turnaround time
• NRE cost of one to three masks (instead of ~30 masks used for Standard Cell customization)
• Performance: compatible with Standard Cell, system clock speed of over 500 MHz
• Optimized internal structures: clocking, scan chain, RAM decoding, power bussing

Designer Benefits:

Design Friendly
Built-in, very low-skew, low noise, clock-tree.
Built-in complete scan test chain.
Built-in support for Post Placement drive Optimization.

Debugging Friendly
Easy reload of Look-Up-Table for debugging purpose.
Full observability by using scan-chain

SoC Friendly
Multiple cores can be tiled and integrated to build the required size of programmable logic.
The LUTs can ALSO be used as RAM memory.

User Interface and Software Features:

• The eASIC™ design methodology matches conventional ASIC flow based on Verilog:
• Synopsys synthesis tools;
• Cadence Place and Route
• Optimized implementation is achieved using proprietary mapper.
• Automatic Test Pattern Generator (SynTest)
• PC and UNIX platforms support

The eASICore™ Value

The eASICore is a user-friendly configurable logic core block that was designed to be embedded easily in SoC applications. It comprises of programmable repeated structure, which allows performing an efficient mapping and layout process for shortening the design cycle. The eASICore offers the flexibility to configure the cells either as logic or as Dual Port SRAM. Featuring self-contained structure, the eASICore enables successful design implementations to be performed rapidly and effortlessly. The debugging is also made simple and easy in the native environment, since the eASICore logic can be re-programmed multiple times as required.

The eASICore is significantly superior in performance and density compared to existing embedded configurable logic cores. Since it utilizes a smaller silicon area, the eASICore offers lower production cost. Moreover, multiple design iterations can be made rapidly and cost-effectively on the fly.