TI's ADSL chip uses a TMS320C6000 DSP core and an ARM 7 TDMI with additional logic for ADSL specific functions and interfaces. The core of the chip has a total gate count in excess of 1 million gates combined with several megabits of RAM. The TI DSP was modeled using VHDL. The ADSL block is written in Verilog and was verified with a combination of behavioral and RTL Verilog testbenches, as well as "C" reference models. The contents of internal memories were compared to the "C" model to gauge results.

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