THE ROLE OF TIMING

Timing is everything, especially in electronic designs. If a signal arrives too soon or too late, data may be lost or the wrong data may be read or written. If a pulse is too narrow, there may not be sufficient time for other circuits to respond. If information is being written to a memory cell, it could be written incorrectly or not written at all. Incorrect timing can prevent transistors from switching properly. In fact, small timing variations caused by temperature or voltage changes can bring an otherwise perfectly functional system down.

For this reason, designers are constantly admonished to limit themselves to synchronous design techniques in which all signals are clocked and all delays are known. Unfortunately, the real world is not a synchronous place. Sometimes designers cannot avoid asynchronous circuits. In other situations, the interaction between two totally synchronous designs may result in unintentional and unexpected interaction. This may happen at the interconnection points of multiple networks that have many users. Thus, designers must always be aware of timing issues, even when doing synchronous designs, because the accurate prediction of timing is critical to a successful application.

Toward this end, virtually every integrated circuit on the market today comes with a data sheet that is full of detailed timing parameters. Designers use this data to ensure that the pulses are wide enough, that setup and hold times are met, and that data are output within some minimum or maximum amount of time. Although designers take a great deal of care to get the timing of every design correct, extraneous factors over which the designer has no control can cause problems. Delays vary with temperature, voltage, and even with minuscule variations in the process technology and lithography used to fabricate the integrated circuit. A decreasing temperature or an increasing power supply voltage can make propagation delays shorter. A lower voltage, as might happen in a battery-operated system when the battery gets low, can cause delays to be longer. Slight process variations during device fabrication can alter the device's transistor parameters, capacitance, and resistance, also affecting its delays.

All of this leads to uncertainty, and designers must work hard to accommodate this uncertainty, while achieving robust functionality and the best performance possible. Vendors of masked ASICs, microprocessors, memories and discrete devices provide designers with abundant information about how the timing of their products can vary under a wide range of temperature, voltage and process variations. Designers use this information to simulate the performance of the circuit under a variety of conditions, so they can identify and resolve any timing problems.

FPGA Vendors Provide Only Worst Case Models - The glaring exception to this rule is the vendors of FPGAs, who provide models based only upon worst case timing parameters. Since designers can use actual programmable silicon to check out their designs, this might seem like a reasonable approach. However, it is impossible to verify all operating corners of a design using only a simulation at the worst case corner and a silicon sample. This is because best case and even typical specifications can cause timing problems. For example, if the width of a pulse controlling the write function of a memory becomes narrower during variations in operating environment, a memory cell may not have enough time to reach a high enough voltage to store the correct data. Either the data won't be stored at all, or it will be corrupted. A memory with the wrong data usually leads to catastrophic results.

Better Models Lead to Better Solutions - On the other hand, modeling the typical and best case timing parameters can help a designer to improve the design. Imagine that a particular circuit cannot meet the worst case timing parameters provided in the FPGA vendor's model. The design might have to be segmented into parallel elements to improve performance, requiring more silicon and a more complex design. The extra silicon will cost more money and consume more power. However, the typical delay, if it were known, might be perfectly acceptable. If the designer can control the voltage or temperature environment in which the system will operate so it will never reach the worst case conditions that cause failure, then he or she can get the desired performance from the existing design.

Another means of solving the problem might be to take routing resources from another circuit with less critical timing to improve the routing of the circuit with the longer delay. Unfortunately, without complete timing and routing data at all operating corners, it is impossible for the designer to fully evaluate the options.

ASIC MODELS

ASIC vendors provide much more robust simulation models that include the minimum, maximum and typical delays for the circuit under a wide range of temperature, voltage and process variations. ASIC customers demand extremely accurate modeling because any error in an ASIC is a very costly proposition. If there is a timing error in an ASIC, it must go through a re-spin, costing many weeks and thousands of dollars. Since programmable devices can be reprogrammed when these errors are located, FPGA vendors feel that they can get away with providing less robust timing models.

Unfortunately, when an FPGA design, with marginal timing, under certain conditions, happens to be one of several thousand FPGAs in a large network of several thousand routers, reprogramming is not that easy. Just locating the router with the problem is extremely difficult. Figuring out which FPGA is at fault is very challenging. Once that FPGA has been located, figuring out what the problem is, where it is located on the FPGA and how to solve it can take weeks. The cost of having a large network down, can be hundreds of thousands of dollars per hour. The network engineer at the location where the router resides is not trained to diagnose timing problems in FPGAs. Thus, although it might seem that it is not as important to have accurate timing information about programmable devices, the fact is that once the end-product is in the hands of the end-user, troubleshooting and fixing failures caused by marginal timing is exceptionally difficult. Having those problems occur at all is very bad for customer relations. This is why ASIC designers put so much effort into identifying and solving timing problems before the ASIC is fabricated. It is surprising that FPGA vendors have not considered doing the same.

Increasingly, FPGAs are being used instead of masked-ASICs in medium gate density, low volume, or short product life cycle designs. Huge NRE costs, large minimum orders and long lead times put masked-ASICs out of reach for many designs. In many cases, customers tolerate the fact that FPGA prices are four to five times as expensive as ASICs to gain the flexibility provided by FPGAs. In other cases, there isn't any other option because the ASIC vendors won't accept designs that don't sell in very high volumes. Unfortunately, because of the lack of robust timing models, the designers who use FPGAs for production are limited in their ability to simulate and improve their designs.

CLEAR LOGIC'S SOLUTION

Clear Logic has developed a family of link-configured ASICs that bridges the gap between ASICs and FPGAs. Clear Logic's ASICs are socket-compatible with Altera^® FPGAs, which serve as the ASIC prototype. The FPGA prototype bitstream is directly migrated to the Clear Logic ASIC implementation using Clear Logic's innovative link-configuration technology. There are no NRE charges, no minimum orders and no lengthy fabrication cycles. Free, configured ASIC samples are shipped to the customer within two to three weeks of Clear Logic's receiving the bitstream file. Production quantities are available within four to six weeks. This sample and production turnaround is comparable to that of FPGAs that are preprogrammed by a distributor. Although Clear Logic ASICs offer the advantages of design flexibility and turnaround of FPGAs, they have ASIC pricing, costing less than 1/3 the price charged for FPGAs of similar density and functionality.

Clear Logic also offers robust simulation models that are comparable with those offered by ASIC vendors. The front-end of the design flow for a Clear Logic ASIC is the same as that of a design implemented using an FPGA through the generation of the bitstream. The designer uses the FPGA design tool of his choice to do the design, and then generates the bitstream. He or she submits the bitstream to Clear Logic's web site, www.clear-logic.com. Based on the bitstream, Clear Logic generates a Verilog simulation model of the device that includes typical, minimum and maximum timing parameters for the customer's design. The model can be used with any Verilog simulation tool, such as Synopsys^TM VCS or Cadence^® Verilog^® XL, to do as many corner simulations as necessary to ensure that the design will work in its operating environment. Once the designer is satisfied with the simulations, Clear logic uses the final bitstream to configure a Clear Logic ASIC, delivering free samples within two to three weeks.

Simulations of Clear Logic ASICs differ markedly from those done using the models generated by the available FPGA design tools. Altera's MAX+PLUS^® II provides only the worst case timing parameters in its models. Although worst case parameters are sufficient in some situations, there are situations in which the design could be blind-sided by the limited information. Two examples follow.

Delays Can Be Too Short — Designs frequently require pulse generators to ensure that a particular voltage is reached and held long enough for some activity to take place. A common example of this is writing to a memory cell. The memory cell must be given enough time to reach a particular voltage for the data to be written properly. If the pulse is too narrow, either the memory cell won't be written to, or it will be written incorrectly. If only worst case propagation delays are available for the simulation, the designer will not be able to simulate a faster delay that may result in a pulse that is too narrow.

For example, suppose the D flip-flop of a one-shot pulse generator needs a 3.0 ns wide pulse width to feed its output back to its clear input. Simulating this circuit using a standard FPGA model from Altera with worst case timing parameters shows a pulse width of 5.8 ns. This delay leaves plenty of margin for the 3.0 ns pulse. However, when using Clear Logic's model to do the same simulation, the designer sees a pulse width of 4.92 ns with worst case parameters, a typical width of 3.69 ns and a minimum width of 2.7 ns. The worst case and typical delays still allow plenty of margin for the one-shot pulse. However, the simulated minimum pulse width of 2.7 ns may be too short. The one-shot pulse will not be wide enough to reliably operate the next circuit in the sequence. The system may fail or suffer erratic operation.

Using the limited model available from the design tools provided by FPGA vendors, the designer would not be aware of this potential problem. In an operating environment with cool temperatures, increased power supply voltage, or with a device from a particularly fast manufacturing process corner, the system may fail. If the designer doesn't have information on the shortest delays, he or she will not be able to detect this problem.

Clear Logic models provides designers with the information needed to identify the potential for this type of problem and correct it.

Worst Case Delay is Too Long -- Suppose two flip-flops are wired directly to the same clock with no added delay. One flip-flop has the input signal tied directly to the data input, but, due to the routing, the second flip-flop has a large delay between the input signal and the input of the flip-flops. The circuit delay will have to be short enough for the signal to travel the distance to the second flip-flop during the same clock cycle as it gets to the first flip-flop. Simulating this circuit using an FPGA model, the 4.5 ns delay required to meet the setup time is violated by the model's worst case 5.8 ns delay. Based on this simulation, the designer will have to redesign the circuit, possibly using additional silicon to pipeline the circuit, in order to meet the setup time. There is no way for the designer to know just how much re-design effort must be expended because there is no other timing information available.

Using the Clear Logic model to simulate this same example shows that, although the worst case delay of 4.92 ns is still too slow, the typical delay of 3.69 ns provides plenty of margin to meet the 4.5 ns setup time. If the system temperature and supply voltage variation can be controlled so that the system will never be in the worst case environment, the designer may be able to use the design as-is and no extra design work is required. Of course, this would only be attempted when there is no other reasonable way to design over the normal operating environment.

Another example is when the placement and routing of the design inadvertently create a critical path that violates a setup and hold time. If the designer has complete information about nearby circuits, he/she may be able to take routing resources from a second circuit with a lot of timing margin and use it to improve the routing of the circuit with the unacceptable delay. However, without more robust timing information, the designer has no way of knowing which tradeoffs are possible. Clear Logic's models provide this information.

Preserving the Hierarchy - Frequently the easiest way to correct a timing problem is to manually re-route part of the circuit or go back to the floorplan and move some elements around to improve their routing. In order to do this, the designer must be able to relate the timing problem to its physical location and routing on the chip. This is virtually impossible using the simulation models provided by Altera's MAX+PLUS II tools because these models are "flat". They have been stripped of any hierarchy that shows the look up tables, embedded array blocks and routing. The model consists entirely of a hopelessly confusing list of AND, OR and NOR gates, with no means of tracing them back to the physical design. The typical output of such a model is shown below:

//
`timescale 100 ps / 100 ps

module inverter (
     in,
     inb);

input in;
output inb;
supply0 gnd;
supply1 vcc;

parameter SDFFILE = "inverter.sdo";
initial $sdf_annotate(SDFFILE);

wire
   \inb~1 , N_8, N_9, N_10, N_11, N_12, N_14, N_15, N_16, N_17, N_18, N_20;

TRIBUF TRIBUF_2 ( .Y(inb), .IN1(N_8), .OE(vcc) );
DELAY DELAY_3 ( N_8, N_9 );
XOR2 XOR2_4 ( N_9, N_10, N_14 );
OR1 OR1_5 ( N_10, N_11 );
AND1 AND1_6 ( N_11, N_12 );
INV INV_7 ( N_12, \inb~1 );
AND1 AND1_8 ( N_14, gnd );
DELAY DELAY_9 ( \inb~1 , N_15 );
XOR2 XOR2_10 ( N_15, N_16, N_20 );
OR1 OR1_11 ( N_16, N_17 );
AND1 AND1_12 ( N_17, N_18 );
DELAY DELAY_13 ( N_18, in );
AND1 AND1_14 ( N_20, gnd );

endmodule

Looking at this model provides absolutely no clue as to where a particular node may reside in the design. Thus, the designer has very little guidance regarding what to do about a simulation that doesn't meet the design's constraints.

Clear Logic models preserve the design hierarchy, showing the actual look-up tables (LUTs), SRAM embedded array blocks (EABs), and actual time delays along the wires used for routing. The Clear Logic model of the same circuit is shown below:

initial
   $sdf_annotate("inputs.sdo");

LUT_2C_1_8_5_1 i_n2529 (.D1(~n768),
      .D2(~n527),
      .D3(~n1547),
      .D4(~n2523_1),
      .CASCADEIN(VSS),
      .CARRYIN(VSS),
      .REGFB(~LEREG_1_8_5_1),
      .LECAS(n2529),
      .CASCADEOUT(CASOUT_1_8_5_1),
      .CARRYOUT(CAROUT_1_8_5_1),
      .NCONFIG(NCONFIG));

LUT_2C_1_8_13_1 i_n2526 (.D1(VSS),
      .D2(~n683),
      .D3(~n527),
      .D4(~n2538),
      .CASCADEIN(VSS),
      .CARRYIN(VSS),
      .REGFB(~LEREG_1_8_13_1),
      .LECAS(n2526),
      .CASCADEOUT(CASOUT_1_8_13_1),
      .CARRYOUT(CAROUT_1_8_13_1),
      .NCONFIG(NCONFIG));

LUT_2C_1_8_15_1 i_n2535 (.D1(VSS),
      .D2(~n440),
      .D3(~n2535_2),
      .D4(~n2535_1),
      .CASCADEIN(VSS),
      .CARRYIN(VSS),
      .REGFB(~LEREG_1_8_15_1),
      .LECAS(n2535),
      .CASCADEOUT(CASOUT_1_8_15_1),
      .CARRYOUT(CAROUT_1_8_15_1),
      .NCONFIG(NCONFIG));

Using this model, the designer can locate exactly where the timing problem has occurred, go back to his FPGA design software, and change the floorplanning or manually re-route part of the design to correct the timing problem. The four numbers after the element identification (in this case, LUT_2C) precisely identify the location of that LUT. The first number connotes the left (1) or right(2) side of the chip. The second number represents the row in which the LUT resides, and the third number represents the column in which the LUT resides. The fourth number identifies which one of the eight LUTS residing in that location is this one. Thus, the first mentioned LUT in this example is the first LUT, in the eighth row and fifth column, on the left side of the chip. If the designer wants to make any change, he/she knows exactly where to go in the physical design.

Since the hierarchy is preserved by the Clear Logic models, the designer may also move up and down the hierarchy of the design from within the simulator's waveform viewer. This is not possible with the models provided by FPGA vendors.

DESIGNERS CAN MOVE DIRECTLY FROM FPGA PROTOTYPE TO ASIC

Since Clear Logic ASICs are fabricated using a different process and a different architecture than the prototype Altera FPGAs, the simulation results from Clear Logic models are not applicable to designs implemented in Altera's programmable parts. They apply to Clear Logic devices.

However, prototype designs done using FPGAs from Altera can be simulated using Clear Logic models and immediately migrated to Clear Logic ASICs. Clear Logic migrates the designs to its ASICs directly from the FPGA bitstream, at the Clear Logic factory. Design migration is automatic and takes less than an hour. Clear Logic can manufacture different customer patterns on a single wafer. As a result, there are none of the NRE charges or lengthy fabrication cycles that one would expect with a conventional masked ASIC. Clear Logic emails robust simulation models to the customer within 24 hours of receiving the bitstream. The customer may simulate the design thoroughly, make any necessary design changes, and resubmit to Clear Logic for new models.

Once the designer is satisfied with the simulations, Clear Logic will ship sample devices, free of charge, within two to three weeks. There are no minimum order quantities and production quantities are available within four to six weeks of receiving the order.

There is no design "conversion". All the designer has to do is submit the bitstream to Clear Logic's web site, www.clear-logic.com. This process takes less than five minutes. Clear Logic will ship configured ASICs within three weeks. These ASICS will function identically in the same socket as the programmable prototype. The Verilog model from Clear Logic gives a true simulation of the operating margins of the Clear Logic ASIC.