Observers of the semiconductor industry cannot help but be impressed by the relentless advance of technology. As manufacturing technologies improve, and provide continuously lower cost, increased density parts, design teams in their intensely competitive markets, strive to take advantage of the technology with ever increasingly complex devices. In devices as common as cell phone handsets or camcorders it is the norm to see microprocessors, DSPs, major blocks of functionality all on the same device. About the only technology that is yet to be integrated in these multi-million gate, system-chip developments is reprogrammable logic. This is quickly becoming the next target for system-chip integration.

Embedded programmable logic offers the promise of reducing project schedules by implementing high-risk design blocks so that during chip bring up, designs can be quickly re-programmed and modified without the long, costly process of redesigning new versions of silicon. Embedded programmable logic also enables field upgrades of complex algorithms or of blocks implementing protocols for evolving standards. (See Figure 1) As process geometries continue to shrink and engineering, mask and prototype silicon costs go up, embedded reprogrammable logic will enable multiple product versions to be built from a single die, leveraging those costs over multiple products.

Figure 1 - Programmable Logic Cores implement high risk control logic and blocks which are likely to change

There are many issues that need to be addressed by design teams to integrate programmable logic in system chips. Integration of reprogrammable logic requires novel application of tools and systems. Reprogrammable logic by its very nature must be uniquely handled at each stage of the design process. The right set of models and data must be available for each step from synthesis, through layout, to full chip timing analysis and simulation (Figure 2). The key requirements for embedded programmable logic must include the following:

• Scalable programmable gate capacity and I/O bandwidth with support for implementing multiple programmable blocks on a single chip

Figure 2 - The right set of models and data for embedded reprogrammable logic must be available for each step of the chip development process

Programmable logic typically consists of large arrays of programmable elements and corresponding routing resources in sufficient quantity to enable virtually any possible interconnection paths. Consequently, no more real estate should be consumed by programmable logic than is necessary for the critical functions for which reprogrammability is essential. For this reason, the programmable logic should consist of cells that are scalable into configurations appropriate for the problem. In addition, there needs to be sufficient cell I/O to fit in the intended custom or standard cell design. Generally programmable logic will be applied in multiple areas of a chip design to suit different project needs. This further drives the need for scalable capacity, but adds the additional burden of having flexible programming and chip test structures and strategies as part of the core technology.

• Silicon-efficient support for both control and datapath functions

Due to the large area of programmable structures relative to custom or standard cell logic, the programmable logic cores must be efficient in mapping both control and datapath functions. Often in the emerging system chips being developed for consumer or communications applications, there is considerable signal processing or encryption or other complex algorithmic functionality that is continuously improving, and therefore desirable to upgrade periodically. These types of functions are best implemented in ALU based structures, as opposed to traditional programmable logic look-up table based structures. The relative area differential can easily be 2:1 in favor of ALU structures. Again the area expense of programmable logic drives this consideration.

• In-field reprogrammability

One of the primary drivers for including programmable logic into either systems or system-chips is the reduced support cost and potential competitive advantage that is provided by field reprogrammability. The above mentioned flexibility to improve or upgrade complex algorithms within already shipped products may set one product considerably apart from others. The basic programmable technology must therefore be reprogrammable, and complemented with software that is capable of mapping new and improved designs into the existing programmable logic structures (Figure 3). Further, we have seen that as these system chips become more common, more and more critical issues arise when design problems are uncovered after products have begun shipping. There have been several recent examples where publicized device bugs have cost hundreds of millions of dollars in recalls, and stock prices for new, emerging companies have dropped dramatically even when low volumes of product have shipped. Consequently, field reprogrammability is a key issue that must be addressed in such a design program.

• Standard CMOS process and design that is easily portable to multiple foundries

Figure 3 - Post-Silicon Programming Flow

Today's chip sourcing environment dictates that maximum flexibility be designed into a new part for manufacturing flexibility. Merchant semiconductor companies and ASIC companies with their own fabs are frequently aligning themselves with other comparable companies and even IC foundries to assure adequate capacity. The ability to easily migrate a design to a new process or to implement the embedded programmable logic in a new design that might be fabricated on a new process requires that the original design use fairly standard CMOS processes and be constrained to layers of routing compatible with the potential re-targeting processes.

• Synthesizable models of the test and programming interfaces

Two of the key issues in designing system chips with embedded programmable logic are testability and programming the embedded programmable blocks. Since every design is somewhat different, there needs to be flexibility in the design of the interfaces between the embedded block's test and programming circuitry and that of the rest of the chip. The ideal way to provide this flexibility is to develop the interfaces as soft macros to be embedded into the non-programmable logic circuitry. This methodology will further provide the flexibility to develop different interfaces as appropriate for different designs.

• Complete Built-in Self-Test capability and support for integration within overall ASIC test methodology

The entire test methodology for the embedded programmable logic blocks needs to be integrated with the rest of the chip test strategy to minimize test time. All embedded programmable logic pins are consumed by internal interconnect within the chip design. Consequently, a methodology like BIST needs to be employed in which a finite number of pins can be reserved within each separate block of programmable logic to be integrated with the test structures of the rest of the chip or brought to the chip boundary for fast, parallel testing of the programmable logic.

• Support for the synthesis, simulation, timing analysis and physical design tools of the leading ASIC EDA vendors

No programmable logic core can be embedded within a system-chip unless it has associated libraries and models supporting the leading design tools for each step of the design process. There needs to be synthesis support for the architecture for mapping RTL building blocks efficiently in the programmable logics core elements. Once a design block is mapped into the programmable logic elements, there must be tools to generate simulation models and netlists that can be back annotated to the simulation environment to verify that the mapped design meets the original RTL intent. Programmable logic needs to be carefully characterized for timing closure in the context of the entire chip. To obtain characterization at the physical design level in a repeatable methodology, the physical layout of the programmable blocks needs to be fixed like other blocks of the design. For this reason, each design team will require a representation in GDS II format for the layout tools they are employing.

• Architecture-specific synthesis libraries

To maximize the efficiency of the programmable logic array in both area and performance, there must be synthesis libraries that can aid the mapping to the specific architecture of the programmable logic being employed. To the extent possible, these libraries should be complemented by timing driven placement algorithms, and even architecture specific synthesis tools.

• Accurate timing models and an effective methodology for achieving timing closure within the context of the entire chip

Achieving timing closure is the most critical part of any system chip development project. Just as it is necessary to have a post-mapping logical representation of the design in programmable logic elements for logic verification, there needs to be a corresponding post-layout extraction of accurate timing models and data for whole-chip static timing analysis and logic simulation with timing. Typically these timing extraction tools will need to produce files in SDF format for the conventional tools being employed today.

• GDS II frame layouts with support for ASIC power and feed-through routing methodologies

With the size of the programmable arrays for a given gate complexity being an order of magnitude larger than custom or standard cell logic it is essential that the layout make allowances within the GDS II for power and feed-through routing.

Identifying the problems can be the biggest obstacle to surmount when introducing new technology.

Like many transitions and inflection points in technology, implementing embedded programmable logic presents challenges that are readily overcome where the need drives engineering teams to make the necessary shift to put new technology to use. The solutions, though non-obvious at first blush, are well within the reach of most SoC and ASIC design teams today.

Adaptive Silicon has proven, in its work with LSI Logic, embedding programmable logic can be achieved within large system chips. As described in this paper, some modification to the design process is necessaryżbut these are not related to specific EDA tools or models, but to the specific use models and treatment of that design data. Only a process that systematically integrates the programmable logic into the full chip design and test methodologies is acceptable.

As with any new technology the role of embedded reprogrammable logic will evolve as design teams learn to adapt to the technical and business implications this flexibility provides. Reprogrammability within ASICs and ASSPs introduces a discontinuity in the current competitive environment between ASIC/ASSP vendors and discrete reprogrammable logic vendors, but that is another story.