ASIC Main | Archives

There is widespread agreement that IC verification engineers are facing an ever-worsening verification challenge. Moore's Law has now governed the parameters of electronic design for over three decades. As the limits of silicon design double every 18 months, a new reality is here today—the reality of verifying what can be designed. In fact, today's integrated circuits are yesterday's complex systems. The ability to verify designs adequately has not kept up with the increasing complexity driven by Moore's Law. As this verification gap widens, the cost of making a mistake is escalating. Market windows are shortening. Tooling charges are approaching $1 million or more. One error can mean the difference between success or failure of a product. Designers cannot afford to make a mistake.

Click here for the full Tech Note.

Home    Product of the Week    App Notes    Tech Notes    Newsletters   

		Click here to get your listing up.