Increasing the clock frequency can require a higher supply voltage that increases the power consumption exponentially. VLIW processors enable increased performance at lower clock speeds, but they are expensive from a total system point of view since they cost more and require substantially more program memory to store the larger instructions. Larger memory results in higher cost and greater power consumption, as well as a larger footprint design. Adding a second processor (e.g., for speech processing) again increases the cost, size, and power drain of the end-product. To wit, all of these traditional solutions end up destroying the most important competitive advantages of the phone—low cost and long standby and talk times.

This inevitable trade-off between power and performance suggests that the traditional approach of using off-the-shelf DSP processors and cores may not be suitable when performance and cost and power consumption are equally important. Even the lowest power versions of standard DSPs consume a lot of power when the clock frequency is high enough. Power consumption of only 0.5 mW/MHz translates into 200 mW with a 200 MHz clock. A handful of standard DSPs that are fabricated in extremely small process technologies can operate with a fast clock and low power consumption. However, the processes and the devices are extremely expensive, violating the low-cost rule for handsets.

Adelante Technologies, the result of a merger between Philips-DSP Division and Frontier Design, a leading DSP IP and EDA vendor, is currently developing DSP solutions that solve these challenges. Adelante's Galaxic™ DSP Technology provides digital signal processing solutions that allow performance to be radically accelerated while maintaining ultra high performance and minimal silicon area.

Adelante Technologies' Galaxic™ DSP Technology
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Adelante Technologies' Galaxic™ DSP Technology is a comprehensive offering of digital signal processing solutions for high-performance, low-power, and cost-sensitive DSP applications. It includes several families of existing and planned DSP cores, associated subsystems, development environments, EDA tools, and design services.

Reconfigurable, Extendable DSP Cores
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Galaxic DSP Technology cores are designed for high-performance, low-power, and low-cost digital signal processing applications in the areas of wireless, digital control, infotainment, and networking. The Saturn DSP Core™ is the first Galaxy DSP family, and is targeted to cost-sensitive, high-volume applications such as wireless handsets and controllers for DVDs, CDs, and hard-disk drives. During the next 18 months, Adelante will introduce additional DSP core families that are optimized for other high-performance, low-power markets.

Lunar™ Subsystem Library
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Integrating a "naked" DSP core into the end-product SoC with external memory, peripherals, I/O, and multiple processors, and then verifying the whole embedded SoC design can be a daunting task that requires up to a year of engineering. All Galaxic DSP cores are pre-integrated with a complete, configurable DSP subsystem that includes on-chip JTAG debug capability, a DMA controller, arbiters, paging, built-in self-test (BIST), monitor, program and data memory, and program and data cache. Interfaces to external memory, peripherals, and processors (including the AMBA bus) are built-in and fully verified.

Atmosphere™ Development Environment
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The Galaxic DSP Technology also includes the Atmosphere™ Development Environment, a comprehensive suite of code development and debugging tools, as well as EDA support for the design of application-specific extensions to both the instruction set and the core's internal hardware. The Atmosphere Development Environment includes all DSP code development tools, including compilers, linkers, debuggers, and profilers. An instruction set simulator (ISS) facilitates early code debugging by providing single-step program execution, the setting of breakpoints, and access to all memory and registers in the core. The debugger also works with the on-chip JTAG run-time debug facilities available on the Lunar subsystem, and allows single-step code execution in the processor itself.

Atmosphere interfaces to development tools from Mentor Graphics (XRAY Debugger, Seamless Coverification Environment, Modelsim HDL simulator) and AXYS (fast behavioral simulation models, MaxSim™ multi-core C/C++ simulation environment).