Design Automation

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Benchtop Engineering -- Design Automation Subsections

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Features

- New - A Preview Of This Year's DAC
The Design Automation Conference people have put together what looks like an outstanding technical program. The program should interest anyone involved in chip design, with emphasis on embedded-software development. (EE Times)
- New - Chipcenter's Dr. Nasser Kutkut Bestows Kudos On National Semi's WebBench Tool
Chipcenter's Nasser Kutkut, Ph.D., asks EEs if they've checked the WebBench on-line design center at National Semiconductor's Web site. 'If not, you ought to check it out and consider using it,' says Kutkut. (ChipCenter: Power)
Modular Macro-Modeling Techniques For SPICE
An extension of macro-modeling techniques makes it practical to create SPICE models of complex parts. The technique takes a modular, visual approach that's highly intuitive. (EDN)

News

Sandwork, Nassda Collaborate on Transistor-Level Design
Sandwork Design, a developer of transistor-level debugging tools, says its WaveView Analyzer analysis tool is now integrated with a full-chip circuit verification and analysis software package from Nassda Corp. (e-inSITE)
Suppliers Tweak Circuit-Board Tools For The Desktop
Adding power to the printed circuit board design desktop, Cadence Design Systems, Altium Ltd., and Electronics Workbench announce upgraded product lines at the PCB Design Conference West. These vendors claim to bring new capabilities to low-cost, Windows-based design suites. (EE Times)
New Library Available for Mentor Graphics Expedition Series PCB Tools
EDA giant Mentor Graphics inks an accord with Optimum Design Associates to make the latter's 2002 ODA Library for Expedition available for use with Mentor's Expedition printed circuit board (PCB) design tools. The production-ready and documented library of symbols, cells (footprints), and a large part database will let new Expedition users reduce the task of library creation. (ChipCenter: WebScan)
PCB Tool To Analyze Differential Interconnects Across Chips, Packages, Boards
Cadence Design Systems is releasing a spin of existing printed circuit board (PCB) design environment with enhancements to its Studio and Expert series flows, and improvements in the SPECCTRAQuest Signal Integrity Expert, Allegro layout, and SPECCTRA autorouter products. Running under Sun Solaris, HP-UX, IBM-AIX, Windows NT, and Windows 2000 platforms, the tools analyze differential interconnects in ICs, packages, and boards. (ChipCenter: WebScan)
Mentor Snaps Up RTOS Vendor
Bolstering its realtime operating system (RTOS) wares, EDA vendor Mentor Graphics acquires Accelerated Technology Inc. The acquisition may be good for designers using systems-on-programmable chips and programmable platforms, because the modifiable RTOS kernel sidesteps modification of the instruction set of the controller in such designs. (EE Times)

Products

- New - Windows, Linux HDL Suite Eases ASIC, FPGA Design
EDA vendor Mentor Graphics enhances its HDL Designer Series front-end design suite to provide better ways to create and manage hardware description languages in ASIC and FPGA designs. The tools run on Windows, Linux and Unix platforms. (EE Times)
- New - Hardware/Software Co-Design
Celoxica Ltd. rolls the next version of its Handel-C-to-hardware design suite for system-level hardware/software co-design. It includes simulation support for ARM and PowerPC processors, synthesis, and area and delay analysis. It includes VHDL/Verilog output, and support for Actel, Altera Excalibur, and Xilinx Virtex II Pro devices. Design entry and synthesis is driven by Handel-C, which is based on ANSI-C extended with concepts for timing, concurrency, flexible-width variables, and resource allocation. (ChipCenter: PLD)
CoWare Announces Interface Synthesis
ChipCenter Technical Editor Murray Disman reviews CoWare's second-generation interface synthesis tools for system-on-a-chip. One of the most difficult problems is finding a bus architecture that gives the best trade-off of performance and power. (ChipCenter: ASIC)
Mixed-Language Simulation Toolset Bows In
Model Technology now has available ModelSim v5.6, a mixed-language simulation toolset that provides up to 2X faster performance, new debug tools, and an improved regression test flow. (ChipCenter: WebScan)
Synopsys Spins Next-Generation Equivalence Checker
Synopsys Inc. rolls out its Formality 2002 next-generation equivalence checker. Its flow-based graphical user interface guides you through the equivalence checking process, reducing the time associated with setup and debug. (ChipCenter: WebScan)
Synthesis Environment Targets PLDs
FPGA maker Altera announces that all its APEX and Stratix device families, as well as the company's Excalibur embedded processor, are now supported by Mentor Graphics' new Precision Synthesis environment. Tailored to the requirements of Altera's PLDs, Mentor's system runs on Windows NT, 98, 2000, and Windows XP platforms, as well as on Sun Solaris and HP-UX computers. (Electronic Business)
SPICE Gets 64-Bit Version
Silvaco has completed development on a turbo-charged 64-bit version of SmartSPICE. Tuned to run on Sun parallel servers under Solaris 8, SmartSpice XL is capable of simulating circuits of multi-million elements with true analog SPICE accuracy. (ChipCenter: WebScan)

Resources

ChipCenter Reference Library
This is your access point for lots of good information covering applications, design tools, consultants, intellectual property, trade shows and standards.
Standards Watch
Here is your access point to the standards world.


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