THE MAGAZINE FOR COMPUTER APPLICATIONS
Circuit Cellar Online offers articles illustrating creative solutions
and unique applications through complete projects, practical
tutorials, and useful design techniques.

EMBED THIS PC

PART 4: Designing Peripherals In
by George Martin

Start ı The Hardware Interface ı The Artwork ı Sources and PDF

This is the last part of my four-part series about designing an embedded ı486-class CPU. Weıve looked at several CPU options and selected DRAM and BIOS flash devices. I pointed you to schematics and other resources to help you get your design off the ground. This month, Iıd like to wrap up the series by taking a look at some peripherals you might like to add.

WHAT TO HOOK ON

With many ı486 designs, you have to plan for a big chunk of memory whether you use flash memory for program storage or an EEPROM or static RAM (SRAM) for data storage. The CPU provides hardware interfaces for DRAM and BIOS EPROM as part of its basic design. Built into its logic is refresh control and wait-state generation.

Some also provide other types of memory, and many offer interface support for the different cards and buses (e.g., PCMCIA, ISA VL, and PCI). All this comes with the PC keyboard, IRDA, and legacy devices, with the exception of a tape deck. If you have a standard card, such as a PCMCIA, the manufacturer has details regarding how to hook that up.

Be careful, though. Not all of these interfaces are available at the same time. Selecting one type of interface often precludes another. You probably canıt have PCMCIA and ISA interfaces both supported by the CPU as a result of pin limitations.

THE SQUARE PEGS

What about unusual or custom interfaces? Many highly integrated devices offer general-purpose pins, which can be used as chip selects or have their address, control, and timing individually configured. Again, you need to be careful. There are never enough of these pins, and the range of address and control is not exactly what you need for your design. Iıve come across this issue several times.

Most chips let you attach memory devices in one of three or four standard ways. If your need is not standard, built-in pins arenıt the answer. Most CPUs also let you access an external bus with all the control signals. With PAL programming tools, you can create your own logic.

Iıve combined CPU pins and customized PAL logic. With this arrangement, the CPU does the major decoding over a large address block. The CPU then controls the bus direction and timing, while the PAL details the interface to a particular device.

I keep referring to a laser light show as a typical design. To run lasers, you need D/A converters that you load with data as fast as possible. If you use D/A converters connected to the bus and mapped in the I/O address space, the design looks a lot like an ISA interface. Assuming that youıre programming in C, the CPU would perform an out instruction, out(address, data), with 16 bits for the I/O address and 16 bits for the I/O data. The compiler translates that command into just a few assembly language instructions, which first loads dx with the address, ax with the data, and then performs an out instruction. Itıs all simple and straightforward.

NEXT