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PART 4: Designing Peripherals In
by George Martin

Start ý The Hardware Interface ý The Artwork ý Sources and PDF

THE HARDWARE INTERFACE

The hardware interface requires the CPU data bus to connect to the D/A data bus. The D/A converter has chip select (CS\) and write (WR\) inputs, which are typically active low. However, donýt make any assumption about the timing of the D/A converter. It needs to be looked at in detail. Devices with no setup and hold-time requirements can interface using a PAL without much worry. Devices with timing requirements on CS\ and WR\ need more care and a register type of design. You will find requirements such as CS\ must be low, 15 ns after WR\ goes high.

This is the stuff that gives you gray hairýor makes you lose your hair. If the timing requirements of your devices differ too much from what the CPU is generating, youýll need to make the PAL a clocked device. If you add a high-speed clock, you can capture and hold the values of the offending pins.

Listing 1 outlines the logic for decoding the ý486 bus signals and connecting a dual D/A converter to the bus. The PAL decodes and controls the bus signals. Keep in mind that this is only an example and doesnýt necessarily give you the best, cheapest, or fastest way of doing things. Youýll find there are a number of ways to connect memory and peripherals in an embedded ý486 design. Just decide which way suits your application best.

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