The SHARC in the C

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THE SHARC IN THE C

Lessons from the Trenches by Michael Smith

Start ı Register Comparison ı Memory Access ı Modify and Volatile Registers ı Length and Base Registers ı Hardware and Software ı Interrupt Handling ı Sources and PDF

REGISTER COMPARISON

You must understand the function and uses of the processor registers before trying to tackle a link between assembly code and C. The available registers (programmerıs model) for the 68K and 21K processors are shown in Table 1. There are as many similarities as there are differences between these processors.

	68K Processor	21K Processor
Integer data registers	D0ıD7	R0ıR15
Floating point registers		F0ıF15, same as R registers
Subroutine return value	D0	R0
Subroutine parameters	On the stack	R4, R8, R12
Address registers	A0ıA7
Index registers		I0ıI7(data memory) I8ıI15 (program memory)
Modify registers		M0ıM7, M8ıM15
Length registers		L0ıL7, L8ıL15
Base registers		B0ıB7, B8ıB15
Volatile registers	D0, D1, A0, A1	R0, R1, R2, R4, R8, R12 I4, M4, I12, M12
Alternate register banks		For Rx, Ix/Mx/Lx/Bx
Frame pointer (convention)	A6	I6, L6 = 0, M5, M6, M7
C stack pointer	A7	I7, L7 = 0, M5, M6, M7
Table 1ıProgrammerıs model of the main registers on the 68K CISC processor and the 21K SHARC DSP processor.

The sixteen 21K data registers (R1ıR15) have essentially the same functionality as the eight 68K data registers (D0ıD7). However, there are many hidden differences. There is an alternate set of 21K data registers available for fast interrupt handling, where as the 68K registers must be saved to slow external memory. The 21K data registers can be used for both for integer (R0ıR15) and floating point (F0ıF15) operations.

The 32-bit addition register-to-register operation, REG0 = REG0 + REG1, is written on the two processors as:

ADD.L D1, D0 (68K)
R0 = R0 + R1; (21K)

The 21K assembler format has a number of other advantages in addition to its C-like characteristics. First, there is no hidden source register like in the 68K syntax. At the end of a long day working on the 68K, I might start wondering if D0 was meant to be added to D1 and stored into D1, or was D1 supposed to be added to D0 and stored in D0?

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Note that the use of the semicolon to signal the end of an assembly instruction permits a single 21K instruction to be written across many lines of code. This free formatting also allows documentation of the instructions describing parallel operations to multiple registers and memory accesses in a single cycle.

Invocation of the 21K processorıs super-scalar capability requires syntax in the form of:

F0 = F1 * F4, F2 = F8 + F12; (21K)

Simultaneous multiplication and addition in a single cycle is available only within certain 21K register banks. This is a limitation of the number of bits available on the 21K program data bus, even though this, at 48 bits, is much wider than the 16 bits of the 68K data bus.

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