THE MAGAZINE FOR COMPUTER APPLICATIONS
Circuit Cellar Online offers articles illustrating creative solutions
and unique applications through complete projects, practical
tutorials, and useful design techniques.

THE SHARC IN THE C

by Michael Smith

Start ı Register Comparison ı Memory Access ı Modify and Volatile Registers ı Length and Base Registers ı Hardware and Software ı Interrupt Handling ı Sources and PDF

MEMORY ACCESS

Figure 2 shows the Data Address Generator DAG1 Block from the SHARC 2106X processor. The eight 21K index registers (I0ıI7) play roughly the same role as the eight 68K address registers (A0ıA7). However, the similarity ends there.

Figure 2ıThis is the Data Address Generation Block (DAG1) on the SHARC 2106X DSP processor. The modulus logic in DAG1 permits hardware circular buffer operations to occur with zero-overhead, but poses problems for the C programmer.

A main limitation of the 68K for DSP operations is the frequent conflicts between data fetches and instruction fetches on a single data bus. The 21Kıs Harvard architecture removes this problem by having both a program memory data bus (for instructions) and a data memory data bus. And, the SHARCıs large on-chip, fast access memory provides more speed.

Even with the Harvard architecture, there will be data/data conflicts when a large amount of data is being manipulated within a tight DSP loop. On the SHARC, this problem is overcome by storing instructions within an instruction cache and allowing data fetches to occur simultaneously down both the program memory data bus and the data memory data bus.

This architectural feature is handled by special C extensions:

int dm data[200]
int pm coeffs[200]

The dm syntax indicates that the data[] array is stored in data memory for fast access through the data memory data bus. The pm syntax indicates that the coeff[] array is stored in program memory for fast access through the program memory data bus.

At the assembly code level, the first bank of 21K Data Address Generator (DAG1) index registers (I0ıI7) allows access to dm memory in parallel with access to the pm memory using the DAG2 index registers (I8ıI15).

Access to arrays stored in memory can be accomplished using either set of DAG registers because of the SHARCıs onboard memory organization. This can be confusing for the inexperienced developer because the introduced bus conflicts are handled transparently by the 21K. The conflict results in additional bus cycles being introduced, rather than the expected high-speed, parallel memory operations!

PREVIOUS • NEXT