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RECYCLE YOUR CODE

Conversion and Optimization Techniques
by Stephen Bowling

Start ý A Code Example ý Optimizing the Code Conversion ý Sources and PDF

Whether you are a seasoned software developer or a beginner, writing good portable code is essential for the reusability of the design. Design reusability has become increasingly important in reducing product design cycles, while reducing the end productýs time to market is still essential. To demonstrate good programming practices that benefit design reusability, the upward migration path towards Microchipýs newest generation of microcontrollers, the PIC18Cxxx family, will be examined here.

The PIC18Cxxx architecture was designed with these goals in mind:

• increased program efficiency
• increased program and data memory address spaces
• increased execution speed
• enhanced peripheral functions that maintain compatibility with other architectures
• source code level compatibility with existing PICmicro code

These features make the PIC18Cxxx family an excellent option for the PICmicro designer who has either run out of program or data memory space, needs faster program execution, or requires the functionality of the enhanced peripherals.

Weýll look at two code-conversion examples using PIC16C7x assembly code. The first example will show the minimum number of steps required to make the source code compatible with the PIC18Cxxx devices. In the second example, Iýll use the source code from the first code conversion and further modify it by taking advantage of some of the PIC18Cxxx architectural enhancements.

PIC18Cxxx ARCHITECTURE

Readers familiar with the PICmicro architecture will find some differences in the operation of the new PIC18Cxxx family. So, before looking at any source code, letýs briefly discuss some of the features of the enhanced architecture.

The PIC18Cxxx device family features a linear data memory map capable of addressing up to 4 KB. The data memory map is subdivided into 16 banks of 256 bytes. The upper 128 bytes of bank 15 (F80hýFFFh) hold the special function registers (SFR). The SFRs are data memory registers that are used to control the operation of the MCU and its peripherals.

The data memory may be addressed using a variety of direct or indirect methods. For direct addressing, the bank select register (BSR) is used. The BSR is a SFR that holds the upper four address bits of the data memory location to be accessed. The lower eight bits of the data memory address are encoded into the program instruction.

Direct addressing can also be performed without the BSR. The MOVFF instruction encodes two 12-bit data memory addresses into a two-word instruction and allows a move from any data memory location to any other location regardless of the BSR value.

Three file select registers (FSR) are available for accessing the data memory indirectly. Each FSR consists of two 8-bit registers (FSR#H and FSR#L), which hold a 12-bit address value. To use the FSR, load the desired FSR with the address of the variable using the LFSR instruction. When an operation is performed on the indirect file (INDF) register, the operation is performed on the data memory location pointed to by the FSR.

There are five INDF registers associated with each FSR that control how the FSR value is modified during the operation. These include the INDF, POSTINC, POSTDEC, PREINC, and PLUSW registers. An operation on the INDF register causes no change to the FSR. An operation on the POSTINC or POSTDEC registers will increment or decrement the FSR, respectively, after a data memory access is performed. An operation on the PREINC register will cause the FSR to be incremented before the data memory access. An operation on the PLUSW register uses the value that is presently stored in the working register (WREG) as a signed offset value for the data memory access.

To ensure that commonly used registers in a given application can be accessed in a single instruction cycle regardless of the current BSR value, a special 256-byte data memory region called the Access Bank has been implemented. The Access Bank consists of the first 128 locations in bank 0 (000hý07Fh) and the last 128 data memory locations (SFRs) in bank 15 (F80hýFFFh). Frequently used variables are located in 000hý07Fh. The use of the Access Bank is selected by a bit in the program instruction. The use of the Access Bank can be manually specified. However, it is best to let the assembler do it for you automatically based on the address of the variable.

The PIC18Cxxx device family has a program memory map, which extends up to 2 MB. The CALL and GOTO instructions in the architecture allow the entire program memory to be reached without the use of paging.

Program instructions consist of one or two 16-bit words. The program memory for the PIC18Cxxx device family is addressed in bytes to make the architecture more C compiler friendly. To ensure that program instruction words are always accessed with the proper byte alignment, the 21-bit program counter (PC) increments in steps of two with the least significant bit set to 0.

The program memory may be accessed on a byte-by-byte basis using table operations, which is useful for the storage of lookup data and calculating program memory check sums. Three registers in the SFR region (TBLPTRU, TBLPTRH, and TBLPTRL) implement a 21-bit table pointer, which points to the desired program memory address. An 8-bit transfer register (TABLAT) holds the value that is to be transferred to or from program memory. The user transfers the data, using table read (TBLRD) and table write (TBLWT) instructions. Depending on the syntax used, the TBLWT and TBLRD instructions can automatically increment or decrement the table pointer.

The PIC18Cxxx device family has an optional two-priority-level interrupt structure with the high-priority interrupt vector at 000008h and the low-priority vector at 000018h. A control bit is available that enables the priority-interrupt scheme, which is disabled by default. This allows interrupts to be compatible with source code written for devices in the PIC16Cxxx family. If priority interrupts are enabled, a high-priority interrupt source may override a low-priority interrupt that is in progress. SFRs are available that set the interrupt priority for each source.

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