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THE RETREAT OF SILICON?

by Tom Cantrell

Start ı One Gate Too Far ı Layout Lament ı Sources and PDF

ONE GATE TOO FAR

Every designer has faced the dilemma. Youıve finally finished your beautifully crafted, artfully elegant, masterfully minimalist design when, "Oh, no! Another NAND gate is needed!"

Actually, these types of gotchas can be a fun challenge, presuming youıve got time for a bit of head scratching. All designers have a war story about the time they ended up behind enemy linesıa gate, bit of memory, or I/O pinıtoo far. Courage, cleverness, and can-do spirit prevail in the form of some inspired hack-around. Victory for our side!

But, save the heroics, because the one-gate is here. Thatıs right, Iım talking about a catalog of Mooreıs lawbreakers from ON (see Photo 1) that integrate a whopping 10⁰ gates.

Photo 1ı"Honey, I shrunk the TTL." The one-gate logic from ON Semiconductor achieves a new low in silicon integration.

So far, the OG lineup consists of a couple dozen parts (see parts list), encompassing the most popular SSI 74xx-type logic functions.

Letıs start by taking a closer look at the 74VHC1GT00 one-gate NAND chip shown in Figure 1. Hey, this high-tech writing gig isnıt so hard after all.

Figure 1ıWhen it comes to a one-gate NAND chip, less is, in fact, less.

In terms of the TTL flavor, the ı1GT00 is based on the VHC-logic family, which is a middle-of-the-road technology that covers a lot of application territory. What it gives away in speed (prop delay of 3 to 5 ns at room temperature and 10 to 15 ns at 85ıC), it more than makes up for in versatility.

The main advantage is that the chips are voltage agnostic when it comes to supply and input/output mixing and matching. Guaranteed operating supply voltage (V_CC) spans a wide 2- to 6-V range. As usual, speed derates as the supply voltage is reduced (e.g., typical room temperature prop delay is 3.6 ns at 5 V_CC and 5.5 ns at 3.3 V_CC).

Inputs feature TTL thresholds (a maximum of VIL 0.8 V and a minimum of VIH 2 V), so the OG can listen to CMOS or TTL as well. Better yet, input protection logic provides over-voltage tolerance. Not only does this protect the inputs up to 7 V regardless of supply, but it also enables an OG to serve as a logic-level translator in mixed voltage applications. For instance, you can connect a 5-V input to an OG running on a 3-V supply to achieve 5-V in and 3-V out level translation.

Outputs are CMOS-compatible semi-rail-to-rail (i.e., VOH > 0.8 V_CC and VIL < 0.1 V_CC fully loaded at IOL = 8 mA). That means, like the input side, the OG outputs are TTL and CMOS bilingual. One nice touch is that the outputs arenıt bothered by a voltage (up to 5.5 V) hanging around when power is shut off (i.e., V_CC = 0 V). Thatıs useful for hot-plug designs or those that use multiple independent on/off power supplies, a common technique for extending battery life.

Not that your battery is even going to know an OG is there with room temperature quiescent supply current of only 2 ıA. Remember that, as with all CMOS, this minimum spec requires the input be held at one of the rails. Power consumption could jump to more than one milliamp if you leave the input floating.

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