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WHAT'S YOUR ENGINEERING QUOTIENT?

Problem 7—Many serial digital audio devices use a 3-wire interface consisting of a bit clock at 64x the sample rate, a square-wave word clock at the sample rate, and a data signal. The state of the word clock (high or low) indicates which channel (left or right) is currently on the data line. In other words, the rising edge of the word clock indicates the first bit of the left sample, and the falling edge indicates the first bit of the right sample.

The ADSP-21xx series of DSPs from Analog Devices have one or two serial ports that are extremely useful for getting serial digital audio signals in and out of the chip. Since this is a 16-bit chip, it requires four words to store a complete stereo sample as defined above. This requires running the SPORT in an "only initial sync required" mode; otherwise, the chip would expect to see a frame sync pulse every 16 bits, and it wouldn't be able to tell where the 64-bit boundaries are.

When initializing the SPORT, the hardware waits for the first clock in which the frame sync signal (the word clock) is high before beginning to transfer data into or out of memory.

The question is, why does this fail about half the time?

The problem is that the SPORT initialization is level-sensitive, not edge-sensitive. If the word clock happens to already be high at the moment the SPORT is started, it will begin transfers immediatly, regardless of which bit of the left channel happens to be coming in at that time.

The solution is to add a small amount of external logic that turns the rising edge of the word clock into a one-clock wide pulse for the SPORT's frame sync pin.

Contributor: Dave Tweed

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