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DESIGNING WITH THE MMC2107

by David Gonzales

Start ý System Overview ý On-Chip Memory Arrays ý Receiving and Servicing Real-Time Interrupts ý Asynchronous and Synchronous Communication ý Measuring, Timing, Creating ý Collecting Analog Information ý System Features ý Sources and PDF

SYSTEM OVERVIEW

Single-chip microcontrollers usually include clock and reset logic, the processor, memory that stores information, an interrupt controller, peripherals, and an external bus interface. The type of peripherals from microcontroller vendors varies depending on the market segment they are targeting. General-purpose I/O ports, timers, serial interfaces, and A/D converters are the most common. Figure 1 illustrates the MMC2107 microcontroller architecture.

Figure 1ýHere you can see a block diagram of the MMC2107.

The processor is the heart of the system. The CPU determines how fast you may compute values, the types of memory access, the method of software development, and whether or not it may be applied to a low-power application. It also defines the arithmetic precision, and the number of registers for temporary variable storage will dictate how efficient the compiled C code will be. Interrupt handling is also important, as the delay between an interrupt request and the time it is serviced is critical in real-time applications.

The MMC2107 implements Motorolaýs low-power micro-RISC M-CORE architecture, which supports full 32-bit integer arithmetic including a hardware multiplier and divider. It uses a four-stage pipeline for efficient execution of streamlined 16-bit instructions, thus permitting low interrupt service latency. There are a total of 45 32-bit registers used for data storage and program context switch information facilitating efficient compiler generated code. Load and store opcodes permit single- or multiple-byte, half-word, and word data movement.

The code has special instructions for determining the source of an interrupt and for storage and retrieval of the program state. The M-CORE processor uses dynamic clock management to automatically power-down internal functions that are not in use on a clock-by-clock basis. It also incorporates three power-conserving operating modes, which are invoked via dedicated instructions.

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