ChipCenter Questlink
SEARCH CHIPCENTER
Search Type:
Search for:




Knowledge Centers
Product Reviews
Data Sheets
Guides & Experts
News
International
Ask Us
Circuit Cellar Online
App Notes
NetSeminars
Careers
Resources
FAQ
EE Times Network
Electronics Group Sites

DESIGNING WITH THE MMC2107


Circuit Cellar Online
THE MAGAZINE FOR COMPUTER APPLICATIONS
Circuit Cellar Online offers articles illustrating creative solutions
and unique applications through complete projects, practical
tutorials, and useful design techniques.

DESIGNING WITH THE MMC2107

Lessons from the Trenches by David Gonzales

Start ý System Overview ý On-Chip Memory Arrays ý Receiving and Servicing Real-Time Interrupts ý Asynchronous and Synchronous Communication ý Measuring, Timing, Creating ý Collecting Analog Information ý System Features ý Sources and PDF

ASYNCHRONOUS AND SYNCHRONOUS COMMUNICATION

Many systems require the asynchronous RS-232 protocol for communicating with one or more host computers, terminals, or other microcontrollers. It allows information to be passed in an industry standard method using a minimum of two wires. The MMC2107 has two on-chip serial communications ports with full-duplex operation. Each has a 13-bit transfer rate selector, a programmable 8- or 9-bit data format, and separate receiver and transmitter interrupt requests with eight different flags for such tasks as framing error detection and hardware parity checking. The receive data is sampled every one-sixteenth of a bit-time to ensure reliable data input into its receive shift register.

An application may require an external chip that performs a special function. Such chips often implement a standard synchronous SPI protocol allowing for high-speed full-duplex transfers of data with the microcontroller. These stand-alone peripherals may range from A/D or D/A converters, serial flash memory, or LCD arrays. The MMC2107 implements a four-wire SPI interface, where it may be configured as a master or slave with a programmable serial clock, which may be an input or output. The receiver and transmitter are double buffered allowing full-duplex transmissions. The output pin may be configured as open drain for wired-OR systems or as a CMOS output with full- or reduced-drive capability. Interrupts may be generated on every eighth clock after the receiver becomes full.

PREVIOUSNEXT


Circuit Cellar provides up-to-date information for engineers. Visit www.circuitcellar.com for more information and additional articles.
For subscription information, call (860) 875-2199, subscribe@circuitcellar.com or subscribe online. ýCircuit Cellar, the Magazine for Computer Applications. Posted with permission.
Click here to get your listing up.

Copyright © 2003 ChipCenter-QuestLink
About ChipCenter-Questlink  Contact Us  Privacy Statement   Advertising Information  FAQ