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WHAT'S YOUR ENGINEERING QUOTIENT?

Problem 1—What is the output of the following digital circuit? A" is the negation of A, the flip-flops are D-type, and assume the outputs are 0 initially.

ANSWER

Problem 2—What is Miller's theorem in circuit theory?

ANSWER

Problem 3—Prove Miller's theorem.

ANSWER

Problem 4—Design a half-adder circuit using just five 2-input NAND gates.

The definition of a half-adder is this: Given two inputs A and B, the outputs are:

Sum = A XOR B

Carry = A•B

ANSWER

Problem 5—What are "key de-bouncing" circuits?

ANSWER

Problem 6—Design a simple circuit with minimal components for de-bouncing a push button switch.

ANSWER

Problem 7—Many serial digital audio devices use a 3-wire interface consisting of a bit clock at 64x the sample rate, a square-wave word clock at the sample rate, and a data signal. The state of the word clock (high or low) indicates which channel (left or right) is currently on the data line. In other words, the rising edge of the word clock indicates the first bit of the left sample, and the falling edge indicates the first bit of the right sample.

The ADSP-21xx series of DSPs from Analog Devices have one or two serial ports that are extremely useful for getting serial digital audio signals in and out of the chip. Since this is a 16-bit chip, it requires four words to store a complete stereo sample as defined above. This requires running the SPORT in an "only initial sync required" mode; otherwise, the chip would expect to see a frame sync pulse every 16 bits, and it wouldn't be able to tell where the 64-bit boundaries are.

When initializing the SPORT, the hardware waits for the first clock in which the frame sync signal (the word clock) is high before beginning to transfer data into or out of memory.

The question is, why does this fail about half the time?

ANSWER

Problem 8—In high-speed digital logic ICs, what is the phenomenon known as "ground bounce"?

ANSWER

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