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DESIGNCON FUSION

by Tom Cantrell

Start ý ASSICs? ý Tail Wags Dog ý Shades of Gray ý You Only Live Twice ý Nice ICE ý Sources and PDF

ASSICs?

What the world needs, and is getting, is a new generation of application semi-specific ICs. These combine hard logic for high-volume standardized functions (e.g., MCU, PCI, and USB) with a measure of field programmability. The major differentiation is how much is done in software (i.e., for chips with a built-in MCU like Triscend and Atmel), how much is done in hardware (ala QuickLogicýs hard-core PCI interface), and how much is done in soft hardware (programmable logic).

Another interesting trend revolves around the emergence of possible gap-filler solutions that fit between the traditional FPGA and ASIC alternative and purport to combine the best of both worlds; the speed and die size of an ASIC with a quick turnaround and the field upgradability of an FPGA.

Consider the latest developments from Chip Express. Chip Express has been around for awhile, known primarily for its novel quick turnaround (five days), laser-trimmed ASIC prototyping service. Recently, it expanded the strategy into the FPGA and ASIC gap with a one-mask, module-based array strategy. This allows volume production and stockpiling of the basic wafers (keeping costs down) while cutting the NRE cost (fine lithography masks arenýt cheap) and speeding the turnaround for a specific chip from several months for a traditional (4ý6 masks) ASIC to mere weeks.

Furthermore, unlike the ever-increasing production commitments demanded by big-shot foundries, Chip Express is happy to take your order for a single wafer. The chips arenýt as fast or cheap as a traditional gate array, but there is plenty of room to fit under the rather spacious cost umbrella afforded by high-end FPGAs.

Now, Chip Express is getting on the hybrid bandwagon too. At the show, it announced a device that combines a complete hard-core Bluetooth subsystem with 100k gates worth of the quick-turn module array (see Figure 1). The hard core itself, known as picoBOOST, is an ARM-compatible processor from picoTurbo that incorporates BOOST Bluetooth technology from NewLogic.

Figure 1ýChip Express is embedding the picoBOOST on its quick-turn, module-based array. The core combines a streamlined pt100 32-bit core from picoTurbo with a Bluetooth baseband processor from NewLogic.

Even historic ASIC über alles advocates are getting on the programmability bandwagon. For instance, did I detect a note of "no mas" in the presentation by John Hesketh of LSI Logic in "The Programmable Logic Core: Enabling the Configurable System-on-Chip?" He described a hybrid ASIC+ programmable logic strategy that combines a traditional gate array with a programmable multi-scale array (MSA) architecture licensed from Adaptive Silicon. Each MSA is made up of hex blocks, comprised of 16 quad blocks, each of which contains four ALUs that can be configured as data paths or control logic.

Figure 2ýEven gate arrays are going programmable. LSI Logic is basing its hybrid product on the Adaptive Silicon ALU array architecture.

I came across another bridge-the-ASCI-FPGA-gap supplier, newcomer LightSpeed, that wraps up the trends nicely. Itýs offering a one-mask new economy gate array that also incorporates a measure of field programmability. The module-based (see Figure 3) array is one-mask programmed, and the portions of the design most likely to change are compiled into RAM reprogrammable PLAs, enabling in-system post production fixes and upgrades.

Figure 3ýOne-mask programmable devices such as the new economy gate array from LightSpeed rely on coarse-grained modules rather than gates.

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