I am building a lighting dimming circuit using Pulse Width Modulation, and a MOSFET n-channel Logic Level for the driving switch. Because I'm driving powerful lamps, it must be able to dissipate 5A at 6 V. My problem is that there is about a 1 V drain-source voltage drop on the MOSFET, which doesn't provide full 6 V power to the lights at 100% duty cycle. Is there any way to reduce this voltage drop, maybe with additional circuitry or a different MOSFET altogether? Or is there a better way to have a solid-state driving switch? Or is this just one of those engineering trade-offs I have to live with?

Dan McCauley

The answers are yes, maybe, and yes, respectively. First, there is a way to reduce the drop across the FET either by changing the driving voltage and/or selecting a different device. Second, maybe there is a better way to do this if you can use a different power supply than 6 V DC. If not, then there isn't a better way to do low power PWM. If you could change to a low voltage AC supply, you could use a triac for dimming. This has some advantages that I will come back to later. For the present, I will assume that you must use the lamps and supplies you described. Finally, no matter what type of solid state switch you use, some switch loss is an engineering trade-off you're stuck with. In order to achieve a less disagreeable trade-off than the one you're facing now, you need to get familiar with some of the peculiarities of MOSFETs and their data sheets.

To begin at the beginning, the first thing you have to do is choose an acceptable value of on resistance (called RDS(on) in the data sheet). The main constraints on your choice here are acceptable power loss, self-heating of the FET, and cost. You will find that RDS(on) is a key parameter of power FETs and that the cost is roughly in inverse proportion to it. Modern FETs are available at reasonable cost with RDS(on) values of 10 to 20 milliohms, which would give you a switch drop of 0.1 V or less at 5 amp. If that's still too high, you could put two or more in parallel. I'll assume for this discussion that a switch loss of 5% would be acceptable. Your total load power is 30 watts at 5 amps, so the maximum acceptable switch resistance is 60 milliohms. You will find (more on this below) that RDS(on) increases with temperature so, to do your initial selection, you should de-rate this by a factor of 1.5 to 2.0 and look for a switch in the 30 to 40 milliohm range.

You wrote that you were using a logic level FET. Here is where you run into one of the quirks of the data sheet that I mentioned above. The term logic level means that the range of gate-to-source voltage at which the FET is on the threshold of conducting drain current lies within the nominal range of TTL, or HCMOS logic families. The upper end of the range is what is usually important. Some manufacturers will call a device a logic level FET if the maximum threshold voltage (called VGS(th) in the data sheet) is no more than 4.0 V; others will restrict this description to devices with a VGS(th) of no more than 2.0 V. In your case, as you will see, lower is better. The important point to remember here is that, at VGS(th), the FET is conducting very little drain current. If you look at the test conditions on the data sheet, you will find that VGS(th) is typically measured at drain currents at or below 1.0 mA. In order to achieve the low RDS(on) you expect you will typically have to apply a gate-to-source voltage several volts higher than VGS(th). Calling these devices logic level FETs may not be a lie, but it's obviously not the whole story.

A good example of this situation (and a device which might be suitable for your application) is International Rectifier's IRL540N. If you look at the data sheet, you will see that the maximum VGS(th) is 2.0 V measured at a drain current of 0.25 mA. The device is advertised as having an RDS(on) of .044 ohms, but if you look at the data sheet you will find that you must apply a gate-to-source voltage of 10 V to achieve this. The dependence of RDS(on) on gate voltage is shown in the following table:

So, you can see that to get the lowest resistance, you need to apply a lot more volts than a logic level. Fortunately, the value is not critical and the gate draws no DC current, so it's relatively simple to get a driving voltage that's higher than your logic levels. The simplest approach is to use a discrete transistor inverter driven by a logic signal with your 6 V as the supply. Figure 1 shows one possibility, using a BPT transistor (don't forget the inversion and be sure the driving gate can source enough base current).

You also could use a small signal logic level FET (e.g., a 2N7000) here but you'll run into the same ambiguity about the required driving voltage. If you are using TTL, the BPT is preferable; if you're using CMOS, the FET is a better choice because the driving gate won't have to supply base current. If the device you choose is like the IRL540N, you can see that the change in RDS(on) between 6 and 10 V on the gate, is not very large. It won't have much affect on your overall efficiency to run this way, though it changes the dissipation in the switch transistor by ~20%. If you want to get the absolute minimum RDS(on) you can include a voltage doubler circuit, like the ICL7660 (from Maxim), to generate a 10-V supply for the inverter. The choice depends on the usual mix of considerations, cost, space, and heat dissipation in the power FET.

The next question you have to consider is self-heating in the FET. The most obvious source of heat is the DC dissipation when driving the load at 100% duty cycle. As I noted above, RDS(on) is temperature-dependent; it has a positive temperature coefficient. This makes it difficult to calculate the junction temperature directly, but a few iterations will usually give an acceptable result. For example, the IRL540N has an RDS(on) of about 2.0 times its room temperature value at a junction temperature of 140ý C. The load current will be essentially unchanged, so the junction dissipation at this temperature will be 2.2 W. The thermal resistance of the IRL540N is listed as 40ý C/W for standard PC mounting so, at 2.2 W, its junction will be ~88ý C above ambient. Thus, the assumed conditions would occur at ~52ý C ambient. If this is not an acceptable set of conditions, you can assume a higher junction temperature or reduce the thermal resistance with heat sinking techniques and repeat the calculation. The up-side of the positive temperature coefficient is that if you choose to use two or more FETs in parallel, they will tend to share the current equally if you keep them well coupled thermally.

A word of caution is in order here. First, the specified thermal resistance value makes certain assumptions about how the device is mounted on the PC board. Second, it is usually difficult to forecast the maximum ambient temperature inside your equipment with accuracy. You'll find useful information about mounting surface mount devices in International Rectifier App Note AN-994. For leaded devices, you'll have to turn to heat sink vendors' catalogs for information regarding how to estimate the thermal resistance you can attain. As a general rule, you should allow some generous safety margins in your calculations and then lay out the board so that there is space available to attach a heat sink if you need to. Once you've built the first unit(s), take some case temperature measurements under conditions as close as possible to a normal operating configuration. Keep in mind that the case temperature of these devices is not very different from the junction temperature, so these measurements will give you an adequate indication of whether or not you came close to your thermal resistance target

. A less obvious source of self-heating is the increased dissipation in the FET when it transitions from off to on and vice-versa. The simple driver circuit of Figure 1 will do a good job of turning the FET off quickly, but the turn-on time for the IRL540N will be in the neighborhood of 10 to 20 usec due to the intrinsic capacities of the device. During this time, the peak instantaneous power can rise to about 50% of the total switched load, in your case, 15 W. This is not a problem if your PWM frequency is low because the average power will then also be low. It's a good reason to keep the PWM frequency at or below ~1 kHz, no matter which FET you choose.

You didn't say so explicitly, but I inferred that your lamps are incandescent. If this is the case, keep in mind that the filament resistance is strongly temperature-dependent. You will probably find that the peak current at lower duty cycles is substantially higher than at 100%. Hence, it is possible that the maximum power dissipation in the FET (which is proportional to the square of the rms current) will be higher at some duty cycle other than 100%.

Also, I don't have personal experience with this, but I've been told by more than one credible source that DC operation of incandescent lamps can lead to problems with corrosion and electroplating between the socket and the lamp base, over time. The manufacturer of your lamps should be able to give you more information about this, but it's one of the reasons people generally stick with AC power for incandescent lamp loads and use triacs for dimming control. If you can do this, apart from reliability, you would not need a bulk DC supply so you might come out with a simpler system. On the downside, triacs of any size tend to have a pretty constant forward drop of about 1.0 V, irrespective of the current carried. If you are stuck with low voltage lamps, you'll have a tougher cooling problem than you would with FETs and a significant switch loss to compensate for as well.

You can get more technical information and data sheets at International Rectifier's web site. It has a pretty good parametric search engine, too. The address is www.irf.com. Other manufacturers of power MOSFETs include Siliconix, Fairchild, and On Semiconductor (Motorola). If you want to look at triacs, try On Semiconductor, Teccor, and Powerex. IR doesn't seem to have much in the lower power ratings.

Stanley Schorum