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EXCALIBUR MARKS THE SPOT

by Tom Cantrell

Start ı Soft Machines ı Roots ı GNU Wave ı Price is Right ı Sources and PDF

SOFT MACHINES

The idea of running a soft processor in an FPGA has spawned an entire architectural genre known as "reconfigurable computing." Designers hope to dynamically adapt machine organization to the task at hand, but this is still blue-sky stuff, more likely found in Ph.D. dissertations than in sockets.

Thanks to increasing density, FPGAs have recently started to step up to the plate as ASIC prototypes. A customer planning an ASIC-based System-on-a-Chip (including a CPU core) can try it out in an FPGA. Although the lashup wonıt be able to achieve the full performance or functionality of the final chip, itıs a lot faster than simulation and works well enough to serve as a testbed for further hardware and software development, functional evaluation, and so forth.

Although it would be an exaggeration to consider them processors, FPGAs have enjoyed some success in DSP applications which, with short loops and lots of parallelism, are rather amenable to hardware acceleration (i.e., a little silicon goes a long way).

Thus, itıs the Altera Nios core that I find most intriguing (see Figure 1). Besides the interesting details of the architecture, I think Nios has some profound implications for the way designers do business in the future.

Figure 1ıNios looks like a typical controller, but itıs really just 1s and 0s that configure an FPGA.

Technically, Nios appears to be a straightforward five-stage pipelined RISC in 16- and 32-bit variants. It does have a few bells and whistles such as a barrel shifter and register windows, but otherwise nothing special, which is exactly whatıs special about it. Unlike reconfigurable computing, ASIC prototyping, and other niche soft-core specialties, Nios aims squarely at mainstream embedded apps.

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