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EXCALIBUR MARKS THE SPOT

by Tom Cantrell

Start ı Soft Machines ı Roots ı GNU Wave ı Price is Right ı Sources and PDF

ROOTS

The idea of running a CPU in an FPGA goes way back. In 1994, an app note appeared effectively describing a processor, though even the author conceded that it was little more than a programmable state machine. [1]

Around the same time, local FPGA guru Philip Freidin was crafting his own homebrewed design, the R16 (see Photo 1). Indeed, some of you may have had the pleasure of seeing Philip demonstrate it at a "Roll Your Own RISC" session I ran at the Embedded Systems Conference a few years ago.

Photo 1ıIn the early ı90s, Philip Freidin created the R16, one of the first FPGA CPUs to demonstrate a practical level of price and performance. I love those switches and LEDs!

Recently in the pages of Circuit Cellar, you saw Jan Grayıs excellent article series, "Building a RISC System in an FPGA", describing the xr16, which is freely available for non-commercial use (www.fpgacpu.org). [2] Like Freidinıs design, the xr16 is a minimalist 16-bit RISC with architecture carefully optimized for FPGA implementation. Because tools are the bane of one-off CPU designs, Grayıs work is notable for including a C compiler, a port of Hanson and Fraserıs LCC. [3] Designed with portability in mind, LCC has historically targeted 32-bit CPUs (ıx86, SPARC, MIPS), but Gray was able to compel LCC to generate code for his 16-bit machine as well (see Listing 1).

Listing 1ıHere is an example of the code generated by LCC for the xr16. Notice the implementation of semantically-rich assembly language macro-instructions using lower-level primitives that comprise the native xr16 instruction set.

These and other pioneering designs have demonstrated that a soft-core running in an FPGA can achieve a practical level of functionality, performance, and price.

However, much depends on how carefully and cleverly the architecture is mapped to the hardware. As shown in Table 1, a 16-bit version of Nios uses 13% of a 200k gate APEX FPGA (or about 26k gates), and runs at 50 MHz.

Table 1ıThe Nios core consumes about 20k (16-bit) to 40k (32-bit) gates. Though difficult to compare, this seems a bit high compared to hand-crafted designs, but keep in mind that Alteraıs latest FPGA has 51,840 LEs, equivalent to 1.5 million gates!

Because gate counts are notoriously hard to decipher, itıs easier to think in terms of bang per buck. According to Altera, the FPGA goes for $40 in volume, leaving a processor cost of about $5, which works out to 10 MIPS per buck. For applications that take advantage of its performance, Nios is definitely competitive with conventional embedded micros.

Assessing the success of the Nios design requires detailed review and hands-on evaluation. What seems clear at this time is that the march of silicon will continue to erode the efficiency and performance concerns that remain. For now, the most interesting thing about Nios isnıt the architecture but the strategy surrounding it.

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