|
A State Machine Design for Binary Pattern
Recognition
by James Antonakos
Start ý The
Problem ý Enumeration ý State
Diagram Approach ý A Little Synchronous
Logic ý State Transition Table ý Let
Karnaugh Maps Find the Patterns ý A Hotshot
One-Shot ý The Real Thing ý Other
Implementations ý I Challenge Youý
ý Sources and PDF
A LITTLE SYNCHRONOUS LOGIC
Synchronous logic can be used to implement
the state diagram. Because there are four states, you use just two
bits to keep track of the state number. Thus, 00 is for state zero,
01 is for state one, 10 is for state two, and 11 is for state three.
A pair of J/K flip-flops should be used to maintain the state number,
and youýll need a combinational logic circuit to control the J/K flip-flops.
Table 1 shows the required J/K excitation
values needed to get the J/K flip-flop to change states properly.
For example, to get the Q output to go from a one before the clock
pulse to a zero after the clock pulse, the J and K inputs must be
set to J = x (0 or 1) and K = 1 to obtain the transition. Table 1
is used to help fill in the state transition table.
|
Q before
|
Q after
|
Required J
|
Required K
|
|
0
|
0
|
0
|
x
|
|
0
|
1
|
1
|
x
|
|
1
|
0
|
x
|
1
|
|
1
|
1
|
x
|
0
|
| Table
1ýThe x stands for "donýt care." This signal
may be a zero or a one. |
PREVIOUS
NEXT
Circuit Cellar provides up-to-date information for engineers. Visit
www.circuitcellar.com for
more information and additional articles.
For subscription information, call (860) 875-2199, subscribe@circuitcellar.com
or subscribe online.
ýCircuit Cellar, the Magazine for Computer Applications. Posted with
permission. |