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A State Machine Design for Binary Pattern
Recognition
by James Antonakos
Start ý The
Problem ý Enumeration ý State
Diagram Approach ý A Little Synchronous
Logic ý State Transition Table ý Let
Karnaugh Maps Find the Patterns ý A Hotshot
One-Shot ý The Real Thing ý Other
Implementations ý I Challenge Youý
ý Sources and PDF
LET KARNAUGH MAPS FIND THE PATTERNS
To build the simplest digital machine,
you need to design the circuitry to drive the J/K inputs of each flip-flip
from a set of minimized logic equations. Because there are only three
bits (A, B, and i) to work with, a three-input Karnaugh map can be
easily used to solve for the minimal logic equation. Figure 2 shows
the four Karnaugh maps associated with the J/K input signals, including
the associated solutions. Note that the "donýt care" x
values help minimize the results in each map.
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| Figure 2aýdýExcitation values
from the state transition table are entered into Karnaugh maps
and solved. The equations from each map are Ja = B, Ka = *B,
Jb = I, and Kb = *i. |
Figure 3 shows a schematic of the digital
machine with simplified 0/1 input logic to allow you to enter the
serial pattern using two push buttons (a zero button and one button).
The NOR gate on the QA and QB outputs detects
when the outputs are both low and illuminates the LED to indicate
that the input number is evenly divisible by four. All you need to
do is generate an input bit and clock pulse for each press of the
zero or one buttons.
| Figure
3ýIn the divide by four detector, the two J/K flip-flops
in package U1 make up the state machine. The third flip-flop
controls the state of the current input bit, i. |
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