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MIXED-LOGIC NOTATION

A Tool for Concise Expression
by Bob Perrin

Start • Physical vs. Logical Truth Tables • Logical Interpretation of Physical Truth Tables • Logic Incompatabilities • Drafting and Reading Mixed-Logic Notation • The Terminal State • Sources

DRAFTING AND READING MIXED-LOGIC NOTATION

Drawing schematics is an art the same way mathematics is an art. In the world of mathematics, for a given theorem, there are convoluted meandering proofs and there are succinct proofs. Both are equally valid, but the latter is preferred. Figure 9 contains several examples of both convoluted and succinct graphical expressions of logic equations.

Figures 9a and 9b are both illustrations of the same physical circuit. The circuit generates a bus reset signal (BusReset). The output should be asserted when SystemReset is asserted or when a microcontroller-generated bus reset signal (ıCBusReset) is asserted. This means the bus will be held in reset (presumably a safe state) while the system is being reset and the microcontroller can at any time force a reset.

Many engineers hold fast to the belief that because the 7408 is described as a quad two-input AND gate, the clearest way to draw the physical device is as an AND gate (see Figure 9a).

Figure 9a—This is an example of what not to do. Don’t make reading schematics tough on the reader.

Some engineers don’t seem to understand that a physical device is equally well represented several different ways. Figure 9a is not an uncommon representation of the circuit, nor is it technically wrong. After all, it does describe the operation of the physical circuit.

Let’s examine the logic equations for the homologic circuit shown in Figure 9a. The reader cannot know whether the intended function of the 7408 is an AND or an OR function except by looking at the gate. Figure 9a naturally leads to the convoluted equation:

*BusReset = *SystemReset • *ıCBusReset

which equation reads, "the bus is NOT being reset when the system is NOT being reset AND the microcontroller is NOT commanding a bus reset." Although this is true, it certainly is a meandering way to get the point across. The clever reader might do a DeMorgan’s equivalent on the equation by complementing both sides, then simplifying, thus obtaining:

BusReset = SystemReset + ıCBusReset

which reads, "the bus will reset when the system is in reset or the microcontroller commands a bus reset." Now, I’d say that’s a bit more succinct than the previous equation.

Figure 9b shows how to use mixed-logic notation to clearly express the equation on the schematic. A reader looking at Figure 9b knows the 7408 is being used to generate an OR function. The are no logical incompatibilities to cause complements to be generated. Thus the reader may immediately write the equation:

BusReset = SystemReset + ıCBusReset

Figure 9b—This is physically equivalent to the circuit shown in 9a, but much easier to read.

Always draw the schematic to communicate the logical function of the circuit, regardless of what name the manufacturer gives to the physical device. Figure 9c is an example of a common decoding for a parallel input/output chip (a PIO).

The logic equation is rapidly deduced, and we can quickly see that the PIO is selected when I/O Request (IOREQ) is asserted and A₁₅ = 0, A₁₄ = 1, and A₁₃ = 1. In this example, the intended AND function of the 7420 happened to correspond to the common representation shown on the manufacturer’s datasheet.

Figure 9c—Using one logic-level converter to introduce a logic incompatibility and one logic-level converter to eliminate a logic incompatibility enables us to create a schematic from which you can effortlessly read the Boolean equation of interest.

Figure 9d shows one last example of both a good and a poor graphical representation of the logical operation of the circuit. The schematic with the AND function lends itself to rapid deciphering by the reader. Clearly the RAM is selected when Memory Request (MEMREQ) is active AND A₁₅ = 0 and A₁₄ = 1.

Figure 9d—This shows both an easy to read schematic and a tough to decipher, but all too common, version.

The alternate schematic in Figure 9d represents the identical physical circuit, but the major combinatorial gate (the 7427) is drawn as a NOR gate (an OR function with active-high inputs and an active-low output). This leads to the rather ugly equation:

CS = * (*MEMREQ + A₁₅ + *A₁₄)

which reads, "the RAM is NOT selected when memory is NOT selected OR A₁₅ is asserted or A₁₄ is NOT asserted." Although technically correct, this is a rather obscure way to describe the circuit behavior. The equation from Figure 9d’s AND representation, reads "RAM is selected when memory is selected and A₁₅ = 0 and A₁₄ = 1," which is much clearer.

This result can be derived algebraically from the equation deduced from the OR representation, but why confuse readers with an OR function and hope they’re quick enough to know you really mean AND, and then require them to work algebra? Clearly the best method is to represent the 7427 as an AND function with active-low inputs and an active-high output.

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