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THROUGH THE LOOKING GLASS

Taking a Look at the PIC18Cxxx Series
by David Brobst

Start ý PIC18Cxxx Chips ý Memory ý Data Memory ý Advanced Indirect Addressing ý Deep and Accessible Stack ý Interrupts ý Power-On Features ý Clock Speed ý 10-Bit A/D ý Hardware Multiplier ý Timers ý CCP/PWM ý USART ý I²C Master ý Table Read/Write ý Current Status ý Sources and PDF

INTERRUPTS

The single level of interrupts in the mid-range family were a vast improvement over the no interrupts of the PIC16C5x family. However, there were still problems. Notably, only one interrupt could be serviced at a time, and more severely, you had to manually save all of the context-sensitive registers. The new PIC18Cxxx family sort of addresses this problem.

The PIC18Cxxx family has high- and low-priority interrupts. Each interrupt in the system can be manually set as a high- or low-interrupt priority. In addition, interrupt priority can be turned off. Unfortunately, this is really only a two-level priority system. So if there was a vital interrupt such as an absence of power, this would have to be the high-priority interrupt and all others would be low-priority interrupts.

The other fix allows for fast interrupts. These automatically save the W, STATUS, and BSR registers. This saves the most important registers on a stack not accessible by you and returns them when the fast interrupt exits. Unfortunately this stack is only one layer deep, so a nested interrupt structure could not be supported with all interrupts running in fast mode.

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