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LOGIC DESIGN REVISTED

by George Martin

Start ı A Merger ı Make the Design Synchronous ı Toplevel ı Quadlogic ı Counters ı Catch That? ı Sources and PDF

A MERGER

Iıd like to go a bit further this month with logic design. Specifically, logic design for the more complicated field programmable devices. I wrote about Lattice Semiconductorıs new design tools two months ago. And, a long time ago, I wrote about A quad B converters using PALs for an Ask Us question. This month, letıs put the two together.

A quadrature encoder converts rotary motion to output two signals named A and B. And of course, these two signals can have four values or states. Depending on the direction of the rotation, clockwise (CW) or counter-clockwise (CCW), the states are slanted in one direction or the other (see Table 1).

Typically, A leading B is denoted as counting up and B leading A as counting down. Given a perfect world, the state changes are all uniform.

Letıs design our system for 10-MHz states. That means, at the minimum speed, that each state is nominally 100 ns in duration. So, you could be counting up (or down) at one count every 100 ns. If youıre building a long counter to accumulate the position, then that counter needs to count at the 100-ns rate. By that, I mean that a count has to ripple through all the bits of the counter by the time the next count arrives. And, reading the counter should be done synchronously (more on this a bit later).

In the real world, the encoder is going to stop on an edge, either A or B. So, what could be seen on the inputs is one steady, the other oscillating, and some high frequency. Typically an IC driving the cable is the load, which will set the rate of the oscillations. It would be nice if the hardware had hysteresis to prevent the oscillations, but you had better be able to handle it in the logic.

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