THE MAGAZINE FOR COMPUTER APPLICATIONS
Circuit Cellar Online offers articles illustrating creative solutions
and unique applications through complete projects, practical
tutorials, and useful design techniques.

LOGIC DESIGN REVISTED

by George Martin

Start ý A Merger ý Make the Design Synchronous ý Toplevel ý Quadlogic ý Counters ý Catch That? ý Sources and PDF

MAKE THE DESIGN SYNCHRONOUS

When you design these complicated PALs or FPGAs, the most important step is to make the design synchronous.

You do this by driving the logic with a clock fast enough to capture all the meaningful data on the inputs and present it to the outputs, but slow enough so that the internal logic has a enough time to solve the equations. In fact, this is an easier method than just plopping down the logic and holding your breath hoping the system tests donýt show a timing problem.

The other issue to consider in metastability. This is a legitimate technical problem that exists in all types of logic. The manufacturer defines a setup and hold time for all inputs. These time frames are typically in reference to a clock edge. Iýve included a couple of links for you to read about this subject in the Resources section at the end of this article.

In a nutshell, if an input changes asynchronously to the clock, violating the setup and holding time, then there exists a possibility that the changing input will produce unstable values in the logic. You can reduce this problem by latching all inputs. The output of the latch will be stable but perhaps not what you expected. That is, if an input goes from 0 to 1 just as you latch that input, you could get either the 0 or the 1. Although it is not as desirable, you can design a system that is stable and predictable.

If you were to sample the A and B inputs at 40 MHz, then you should have two valid readings for each of the four quadrature states. Forty megahertz gives you period of 25 ns, and you can find lots of logic devices that are fast enough to meet that speed.

PREVIOUS • NEXT