LOGIC DESIGN REVISTED

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LOGIC DESIGN REVISTED

Lessons from the Trenches

by George Martin

Start ı A Merger ı Make the Design Synchronous ı Toplevel ı Quadlogic ı Counters ı Catch That? ı Sources and PDF

TOPLEVEL

I implemented the interesting part of this design using Lattice Semiconductorıs Design Expert tools. The design consists of three schematicsıtoplevel, quadlogic, and counters.

Taking a look at toplevel (see Figure 1), you see the inputs A_IN and B_IN and two latches for each input. The first latch is for metastability, and the second is used to determine the changes in the values of the A_IN and B_IN inputs.

(Click to Enlarge)

Figure 1ıThe toplevel schematic consists of the inputs A_IN and B_IN and two latches for each input.

If AB were 00 and then became 10, that change would represent one count up. Likewise, if AB were 11 and became 01, that would be one count down. The truth table for counting would look like what you see in Table 2.

OldAB	NewAB	Result
00	10	Up
10	11	Up
11	01	UP
01	00	Up
00	01	Down
01	11	Down
11	10	Down
10	00	Down
00	00	No change
10	10	No change
11	11	No change
01	01	No change
00	11	Error
10	01	Error
11	00	Error
01	10	Error
Table 2ıThis is what the truth table for counting would look like.

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