THE MAGAZINE FOR COMPUTER APPLICATIONS
Circuit Cellar Online offers articles illustrating creative solutions
and unique applications through complete projects, practical
tutorials, and useful design techniques.

LOGIC DESIGN REVISTED

by George Martin

Start ý A Merger ý Make the Design Synchronous ý Toplevel ý Quadlogic ý Counters ý Catch That? ý Sources and PDF

QUADLOGIC

I implemented everything from the table except the error conditions. That implementation is found in the quadlogic schematic (see Figure 2). The inputs to this schematic are A and B and the previous A and B (A_OLD and B_OLD). The outputs are up and down. These are classic signals, which usually go to TTL type counters.

(Click to Enlarge)

Figure 2ýThis quadlogic schematic shows everything I implemented from the truth table.

But as you will see in a schematic farther on, I needed to add logic to convert up and down into down (DN) and enable (EN). So, I should have started with a different truth table (see Table 3).

But, I donýt think this design will suffer from that first choice. Also notice, that I registered the outputs in quadlogic. There is no telling how the logic will fit into the array. Take Up, for example. A good design program would realize that there are four inputs and minimize the logic to derive up. A lesser program would implement the AND gates, then take those four intermediate outputs and route them through the array again to implement the OR function. So, I registered for safety. After you fit the design, the simulation will tell you if these registers are needed.

PREVIOUS • NEXT